Data Access System With Bridge Device For Power Saving
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Solution Overview
Problem
Existing data access systems face challenges in power consumption and access synchronization, particularly as the number of registers increases, leading to complex circuit designs and inefficiencies in power management and synchronization.
Innovation Solution
A data access system and method that generates an access signal with a pulse within a reference clock cycle, using a bridge device to manage the timing of the pulse and reduce power consumption by eliminating the need for continuous clock signals, and employing an address decoding unit to select the appropriate memory bank for data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of registers are used in the system, then the system can handle more data access operations, but the power consumption increases significantly
Solution Approach 1:
The patent implements periodic action by enabling registers to enter sleep mode during idle periods and only activating them when data access is required. The microcontroller controller selectively activates registers based on actual access needs, creating a periodic on-demand activation pattern rather than continuous operation, thereby reducing overall power consumption while maintaining data access capability.
Solution Approach 2:
The patent applies local quality by enabling selective activation of individual registers based on their specific access requirements. Instead of uniformly activating all registers, the system activates only the necessary registers at specific times, creating local variations in power states that optimize the balance between data access capability and power consumption.
2Manufacturing precision
If fine tuning of access clocks is performed to balance skew effects, then data access synchronization is improved, but the circuit design becomes more complicated
Solution Approach 1:
The patent introduces an intermediary mechanism (the controlled clock activation system) that mediates between the microcontroller and registers. Instead of directly fine-tuning each register's clock to compensate for skew, the system uses a centralized clock control approach that activates clocks only when needed, simplifying the circuit design while maintaining synchronization through coordinated clock management.
3Speed
If continuous clock signals are sent to all registers, then data access speed is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic action by sending clock signals only during active data access periods rather than continuously. The system activates clocks periodically based on actual access requirements, creating intermittent clocking that maintains data access speed when needed while dramatically reducing power consumption during idle periods.
Solution Approach 2:
The patent extracts the continuous clock signal requirement and replaces it with selective, on-demand clock activation. By taking out the unnecessary continuous clocking and retaining only the essential periodic activation, the system maintains data access performance while eliminating wasted energy from continuous operation.
Data Source
AI summary
A data access system and a data access method achieving effects of power saving and access synchronization during data access are provided. The data access system includes a data processing unit, a bridge device and a memory device. The data processing unit sends an access request signal to initiate data access of at least one unit data. The access of unit data is completed within a plurality of clock cycles of a reference clock signal. The bridge device generates an access signal according to the access request signal, the reference clock signal and a leading time. A pulse of the access signal is determined by the leading time within the clock cycles. The memory device executes the access of the unit data according to the access signal.