Data Access and Permute Unit for Vector Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital signal processing applications face inefficiencies in performing arithmetic operations on long vectors due to the need for explicit permutation instructions, which increases program size and latency, especially when matching short vector widths of machine hardware to longer vector widths in processor memory or registers.
Innovation Solution
A data processing unit with a register access mechanism capable of performing permutation operations in series with data access and execution, utilizing a crossbar multiplexer stage and opcode-based control for various permutation types, such as roll, sort, shuffle, and broadcast, to efficiently handle vector operations within a single instruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If explicit permutation instructions are used to match short vector widths to long vectors, then vector operations can be performed correctly, but program size increases and latency increases
Solution Approach 1:
The patent combines permutation operations with data processing operations into a single unified instruction. The execution unit integrates both permutation logic and arithmetic logic, allowing the processor to perform gathering, shuffling, and arithmetic operations in one step rather than requiring separate permutation instructions followed by data processing instructions.
Solution Approach 2:
The execution unit is designed with multi-functional capability to handle both permutation operations and data processing operations. A single execution unit can dynamically switch between performing gathering permutations, shuffling permutations, and various arithmetic operations based on the instruction type, eliminating the need for separate dedicated permutation hardware and arithmetic hardware.
2Manufacturing precision
If explicit permutation instructions are used to gather elements from long vectors, then correct data can be supplied to short vector datapaths, but program execution latency increases
Solution Approach 1:
The patent merges the data gathering permutation step and the subsequent arithmetic operation into a single unified instruction execution cycle. The execution unit performs the gathering permutation and the arithmetic computation simultaneously in one pipeline pass, eliminating the sequential delay that would occur if these operations were performed in separate instruction cycles.
Solution Approach 2:
The execution unit performs preliminary permutation setup within the same instruction cycle that triggers the arithmetic operation. Control signals for the permutation logic are generated and executed concurrently with the arithmetic computation, rather than requiring a separate preparatory instruction cycle before the arithmetic operation can begin.
3Ease of operation
If separate permutation instructions are used, then vector elements can be distributed to different locations, but the number of instructions increases
Solution Approach 1:
The patent combines vector distribution (shuffling) operations with arithmetic operations into a single unified instruction. The execution unit performs both the shuffling permutation to distribute elements to different locations and the subsequent arithmetic computation in one operation cycle, effectively doubling the productivity compared to separate instruction execution.
Solution Approach 2:
The execution unit is designed with universal capability to handle various types of permutations (gathering, shuffling, broadcasting) and arithmetic operations through a single multi-functional hardware block. This allows the processor to maintain high operations-per-cycle throughput by avoiding the need for separate dedicated hardware units for each operation type.
Data Source
AI summary
According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand.