Synchronization Using Data Address Field Patterns
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Solution Overview
Problem
Existing logic node implementations in local area networks face inefficiencies due to challenges in synchronization, particularly when slave logic nodes reset or power up during ongoing transactions, leading to potential bus conflicts and incorrect register values.
Innovation Solution
The use of a subset of predetermined patterned data bits in the data/address field of a communications protocol to synchronize transactions, instead of the optional preamble field, allowing for synchronization without preambles and reducing bus load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the optional preamble field is used to synchronize logic nodes, then synchronization reliability is improved, but device complexity and bus load increase
Solution Approach 1:
The patent extracts the synchronization function from the optional preamble field and relocates it to the data/address field. By taking out the preamble's synchronization role and placing it in the data/address field with specific patterned bits (e.g., 0x5555 pattern), the system achieves reliable synchronization without requiring the additional preamble structure, thereby reducing device complexity and bus load while maintaining synchronization reliability.
2Reliability
If the preamble field is used for synchronization, then logic node synchronization is achieved, but bus load increases
Solution Approach 1:
The patent merges the synchronization function with the existing data/address field transmission. Instead of sending separate preamble bytes for synchronization, the system combines synchronization patterns (specific bit patterns in the data/address field) with the regular data transmission. This merging eliminates the need for additional preamble bytes on the bus, reducing bus load while maintaining reliable synchronization of logic nodes.
3Quantity of substance
If synchronization is performed without patterned data bits in the data/address field, then bus load is reduced, but synchronization reliability deteriorates
Solution Approach 1:
The patent applies local quality by introducing specific patterned data bits (such as the 0x5555 pattern) at critical synchronization points within the data/address field, rather than requiring patterned bits throughout the entire transmission. This localized application of synchronization patterns reduces the overall bus load compared to universal preamble fields while ensuring reliable synchronization at the points where these patterns are strategically placed in the data/address field.
Data Source
AI summary
An apparatus for a local area network includes a management communications bus, and at one of a plurality of logic nodes, logic circuitry. The management communications bus is for communication among the plurality of logic nodes, wherein respective node addresses for the plurality of logic nodes are conveyed using the management communications bus. The logic circuitry communicates information in a data/address field of the communications protocol with another of the plurality of logic nodes with reference to a subset of the predetermined set of patterned data bits in the data/address field to synchronize the transactions.