Two-Stage Data Alignment Circuit for Lower Jitter and Clock Skew
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Solution Overview
Problem
Conventional data alignment circuits using four clocks with different phases for parallelizing serial data suffer from degraded jitter characteristics and poor clock skew due to low frequency clocks, especially exacerbated in high-data-count applications like GDDR memory devices, leading to increased noise and circuit size.
Innovation Solution
A data alignment circuit employing a first latch unit using two clocks with the same frequency and diverse phases, followed by a second latch unit using four clocks with a lower frequency and even more diverse phases, reduces the number of clock lines and mitigates jitter issues, while a divider generates the necessary clocks from a Phase Locked Loop (PLL), thereby improving alignment efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If four clocks with different phases are used for parallelizing serial data, then data alignment capability is improved, but jitter characteristics are degraded
Solution Approach 1:
The patent divides the data alignment process into two separate latch units: a first latch unit that handles initial parallelization with fewer clocks, and a second latch unit that performs additional parallelization. This segmentation allows each unit to use optimized clock configurations, improving overall jitter characteristics while maintaining data alignment capability.
Solution Approach 2:
The first latch unit acts as an intermediary between the serial input and the second latch unit. It processes the serial data with a simplified clock configuration and passes the intermediate result to the second latch unit, which then achieves the final parallelization. This intermediary approach reduces the direct burden on the clock system.
2Productivity
If four clocks with different phases are used for data alignment, then parallelization ratio is improved, but clock skew increases
Solution Approach 1:
The patent segments the parallelization process across two latch units with different clock configurations. The first latch unit uses a smaller number of clocks with manageable phase differences, reducing skew accumulation. The second latch unit then builds upon this with additional parallelization, achieving the overall high parallelization ratio without the cumulative skew problems of a single-stage approach.
3Productivity
If more clocks are used for aligning higher data counts, then data alignment capability is improved, but circuit size increases
Solution Approach 1:
The patent segments the latch functionality into two units with different clock requirements. The first latch unit uses fewer clocks to handle the initial parallelization, and the second latch unit uses additional clocks for further parallelization. This segmentation allows the circuit to achieve high data alignment capability for 32 or more data bits without requiring a single large bank of clocks, thereby controlling circuit size.
4Productivity
If more clock lines are used for delivering clocks to latch units, then data alignment capability is improved, but noise increases
Solution Approach 1:
The patent segments the clock distribution into two separate systems: one for the first latch unit and another for the second latch unit. The first latch unit receives clocks from a PLL with fewer phase divisions, requiring fewer clock lines. The second latch unit receives additional clocks with more phase divisions. This segmentation reduces the total number of clock lines compared to a single-stage high-parallelization approach, thereby reducing coupling noise and interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances jitter characteristics and reduces clock skew, minimizing circuit size by using fewer clock lines and addressing noise-related issues, effectively aligning serial data into parallel form with improved reliability and reduced noise interference.
Implementation Method 1
the four clocks are generated by a PLL (Phase Locked Loop)
Data Source
AI summary
A circuit for data alignment includes a first latch unit and a second latch unit. The first latch unit latches serial input data by using a plurality of first clocks with different phases and the same frequency to output latched data. The second latch unit latches the data from the first latch unit by using a plurality of second clocks with a lower frequency than the first clocks and more diverse phases to thereby output parallel data.