Independent Data Arbitration Logic for Interconnect Latency
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Solution Overview
Problem
Existing interconnect logic in data processing apparatuses using split transaction protocols does not efficiently utilize resources, leading to stalling of master logic units waiting for data transfers to complete, despite enhancements for local reordering at slave devices.
Innovation Solution
The implementation of independent data arbitration logic within the interconnect logic, allowing data transfers to occur out of order with respect to address transfers, using address, read data, and write data arbiters to manage multiple transactions efficiently across address and data channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data transfers are prioritized according to the temporal ordering of address transfers, then balanced service to every master and slave logic unit is achieved, but master devices are stalled while waiting for data transfers
Solution Approach 1:
The system performs preliminary actions by buffering data transfers and reordering them before transmission. The reordering mechanism prepares data in an optimized sequence based on current system state rather than strict temporal order, allowing earlier data to be transmitted later and later data to be transmitted earlier when appropriate, thus preventing stalls while maintaining balance.
Solution Approach 2:
The data transfer prioritization is made dynamic rather than static. The system can adaptively change the priority of data transfers based on current conditions, allowing the arbitration mechanism to flexibly reorder data packets. This dynamic approach enables the system to optimize throughput by transmitting data that can be safely reordered while maintaining fairness when needed.
2Productivity
If independent data arbitration logic is implemented, then latency is reduced and throughput increases, but device complexity increases
Solution Approach 1:
The arbitration functionality is segmented into separate independent components: address arbitration logic and data arbitration logic. This segmentation allows each component to operate autonomously with its own optimization strategies, reducing the complexity burden on any single component while achieving overall system performance improvements through coordinated operation of multiple specialized units.
3Productivity
If data transfers occur out of order with respect to address transfers, then resource utilization is optimized, but ordering constraints may be violated
Solution Approach 1:
The system employs feedback mechanisms where the data arbitration logic monitors the state of ongoing transactions and adjusts data transfer ordering based on this feedback. The arbitration mechanism receives information about address transfer status, slave device readiness, and transaction state, using this feedback to dynamically determine the optimal reordering strategy that maintains ordering constraints while optimizing resource utilization.
Data Source
AI summary
Interconnect logic is provided for coupling master logic units and slave logic units within a data processing apparatus to enable transactions to be performed. Each transaction comprises an address transfer from a master logic unit to a slave logic unit and one or more data transfers between that master logic unit and that slave logic unit. The interconnect logic comprises a plurality of connection paths for providing at least one address channel for carrying address transfers and at least one data channel for carrying data transfers, and control logic is used to control the use of the at least one address channel and the at least one data channel in order to enable the transactions to be performed. The control logic comprises address arbiter logic which, for an associated address channel, arbitrates between multiple address transfers seeking to use that associated address channel, and data arbiter logic which, for an associated data channel, arbitrates between multiple data transfers seeking to use that associated data channel. The data arbiter is operable independently of the address arbiter such that the data transfers of multiple transactions can occur out of order with respect to the corresponding address transfers of those multiple transactions. This enables efficient use to be made of the interconnect logic resources.