Data Transport Block Memory Error Protection via Parity and CRC
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Solution Overview
Problem
Modern modem chips, particularly those for LTE, face increasing susceptibility to intermittent memory failures due to higher on-chip memory density and data rate demands, requiring improved error protection mechanisms beyond traditional error correction coding.
Innovation Solution
The implementation of Hybrid Automatic Repeat Request (HARQ) mechanisms combined with cyclic redundancy checks (CRC) and parity bits to provide redundancy and error correction for data transport blocks, allowing for real-time correction of memory errors without violating tight processing deadlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full-blown real-time error correction coding (ECC) is applied to each memory cell, then memory error protection is improved, but device complexity and processing overhead increase significantly
Solution Approach 1:
The patent applies partial error correction by using only parity bits for memory error detection and CRC for transmission error detection, rather than implementing full-blown ECC for each memory cell. This selective approach provides sufficient protection against the specific error types encountered while avoiding the excessive complexity of comprehensive ECC schemes.
Solution Approach 2:
The patent segments the error protection mechanism into two distinct parts: parity bits for memory error detection and CRC for transmission error detection. This segmentation allows each mechanism to be optimized for its specific purpose and enables the system to handle different error types appropriately without requiring a single complex ECC solution.
2Reliability
If complex error correction mechanisms are implemented, then error protection is improved, but processing time and deadline compliance deteriorate
Solution Approach 1:
The patent implements partial error correction using only the necessary components (parity bits and CRC) rather than comprehensive ECC, which significantly reduces processing time while maintaining adequate error protection. This allows the system to meet tight processing deadlines associated with LTE standards.
Solution Approach 2:
The patent changes the error correction parameters by using simplified parity bit schemes and CRC instead of complex ECC codes. This parameter change reduces the computational complexity and processing time required for error correction while maintaining sufficient reliability for the application.
3Productivity
If on-chip memory density is increased to support higher data rates, then productivity is improved, but susceptibility to memory failures increases
Solution Approach 1:
The patent applies preliminary error detection measures by attaching parity bits to data blocks before they are stored in memory. This preliminary protection allows for quick detection of memory errors without requiring complex real-time correction mechanisms, enabling the system to handle high data rates while maintaining reliability.
Solution Approach 2:
The patent introduces CRC as an intermediary mechanism that bridges memory error detection and transmission error detection. The CRC serves as a secondary validation layer that can identify errors that escaped the parity bit check, providing enhanced protection without significantly increasing processing complexity.
Data Source
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AI summary
A method (600) for protecting a data transport block against memory errors and transmission errors includes: attaching (601) a first redundancy section to the data transport block for protecting the data transport block against memory errors and providing the data transport block in a memory buffer; attaching (602) a second redundancy section to the data transport block read from the memory buffer for protecting the data transport block against transmission errors and providing the data transport block for transmission; and invalidating (603) the second redundancy section if an evaluation of the first redundancy section of the data transport block read from the memory buffer indicates a memory error.