Data Buffer Circuit for Multiple DIMM Topology
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Solution Overview
Problem
The maximum operating frequency of dual in-line memory modules (DIMMs) decreases due to parallel loading, and current load-reduced (LR) DIMMs with data buffers are insufficient to handle the bandwidth limitations caused by signal trace branches, leading to reduced data rates and increased reflections in DDR systems.
Innovation Solution
A data buffer circuit element is integrated into a printed circuit board (PCB) to remove trace branches from the memory data channel, using a multiplexer or analogous structure to emulate point-to-point communications between the memory controller and DIMMs, thereby controlling reflections and increasing data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple DIMMs are directly attached to a memory controller, then memory capacity increases, but the maximum operating frequency decreases due to parallel loading
Solution Approach 1:
A data buffer is introduced as an intermediary component between the memory controller and multiple DIMMs. The data buffer receives data from the memory controller and selectively transmits it to different DIMMs, effectively mediating the parallel loading issue and enabling higher operating frequencies while maintaining support for multiple DIMMs
Solution Approach 2:
The data buffer is divided into multiple independent buffers (first data buffer, second data buffer, etc.), each handling data for specific DIMMs. This segmentation allows independent management of data paths to different DIMMs, reducing parallel loading effects and enabling higher operating frequencies
2Reliability
If load-reduced DIMMs with data buffers are used, then the DRAM load is hidden from the bus, but the trace branches still limit the bandwidth of the channel
Solution Approach 1:
The harmful trace branches are extracted or removed from the data path between the data buffer and DIMMs. By eliminating these branching traces, the patent achieves point-to-point connections that prevent bandwidth limitation while maintaining the load buffering capability of the data buffer
3Quantity of substance
If multiple rank DIMMs are used, then memory capacity increases, but reflections increase and data rates decrease
Solution Approach 1:
The data buffer acts as an intermediary that isolates the memory controller from reflections generated by multiple DIMMs. By buffering data before transmission to individual DIMMs, the system reduces reflection effects while maintaining support for multiple rank DIMMs and high memory capacity
Data Source
AI summary
Aspects of the embodiments include systems and devices that include a memory controller circuit element, and a printed circuit board (PCB). The PCB can include a memory module element; and a data buffer circuit element, the data buffer circuit element electrically connected to the memory controller circuit element and configured to receive instructions and data from the memory controller circuit element, the data buffer circuit element electrically connected to the memory module circuit element directly or through a socket, the data buffer circuit element configured to transmit instructions and data originated from the memory controller circuit element to the memory module circuit element and transmit data back to the memory controller.