Data Buffer Circuit Layout for Shorter DDR5 Equalizer Power Lines
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Solution Overview
Problem
In the layout design of DDR5/LPDDR5 data buffer circuits, excessively long connection lines between decision feedback equalization modules and power supplies affect circuit performance, necessitating an optimization of the layout structure.
Innovation Solution
The data buffer circuit structure is optimized by arranging the first and second amplification circuits, decision equalizer, and power modules in the same direction, with the power supply units positioned closer to their respective amplification circuits, reducing connection line lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If elements of the same module are disposed together based on module division, then the layout structure is simplified and manufacturing is easier, but the connection line between the decision equalizer and power supply becomes excessively long, affecting circuit performance
Solution Approach 1:
The power supply module is segmented into multiple power supply units, with each unit dedicated to specific circuits. The first power supply unit supplies power to the first amplification circuit and decision equalizer, while the second power supply unit supplies power to the second amplification circuit. This segmentation allows each power supply unit to be positioned closer to its target circuits, reducing connection line lengths while maintaining manufacturing simplicity through standardized modular units.
Solution Approach 2:
Different regions of the circuit layout are assigned different power supply characteristics. By positioning the first power supply unit closer to the first amplification circuit and decision equalizer, and the second power supply unit closer to the second amplification circuit, each region receives optimized power delivery with minimized connection lengths tailored to local requirements.
2Reliability
If the connection line between decision equalizer and power supply is made shorter to improve performance, then circuit performance is enhanced, but the layout structure becomes more complex and harder to manufacture
Solution Approach 1:
The power supply system is divided into multiple independent units, each responsible for specific circuits. This segmentation enables shorter connection lines to each unit while the overall layout remains organized and manufacturable through standardized repeating patterns of amplification circuits and their associated power supply units.
Solution Approach 2:
The first amplification circuit and decision equalizer are merged into a functional group supplied by the first power supply unit, while the second amplification circuit forms a separate group supplied by the second power supply unit. This merging creates compact functional blocks with short internal connections, reducing overall complexity while improving performance.
Data Source
AI summary
A data buffer circuit structure, a layout structure of multiple data buffer circuits, and a memory. The data buffer circuit structure includes a first amplification circuit, a second amplification circuit, a decision equalizer, and a power module. An output terminal of the first amplification circuit, an input terminal of the second amplification circuit, and adjustment output terminals of the decision equalizer are connected through a signal line. The power module includes a first power supply unit and a second power supply unit. A minimum distance between the first power supply unit and the first amplification circuit is less than a minimum distance between the first power supply unit and the second amplification circuit, and a minimum distance between the second power supply unit and the second amplification circuit is less than a minimum distance between the second power supply unit and the first amplification circuit.