Data Buffering Using Address Pointer and Enable Bit Array

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In computer systems, data buffers are inefficiently utilized due to random transfer of data from CPUs like the AMD K8 processor, leading to wasted resources as earlier data is stored temporarily until later data is transferred in order.

Innovation Solution

A data buffering method using an address pointer and an enable bit array to determine and transfer sub-data in highest priority order, releasing buffer space effectively by enabling and resetting bits to manage the transfer sequence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data are transferred randomly from CPU to bus, then data processing flexibility is improved, but data buffer space is wasted due to ineffective occupation

Engineering Contradiction:
Improvedata processing flexibilityVSAvoidbuffer space utilization
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The data buffer is segmented into multiple buffer lines (first buffer line, second buffer line, etc.), each responsible for storing specific data items. This segmentation allows the system to maintain flexible data processing while improving buffer space utilization by organizing data in a structured manner across multiple lines rather than using a single undifferentiated buffer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each buffer line is assigned specific local quality characteristics - the first buffer line stores first data items, the second buffer line stores second data items, and so on. This local differentiation enables the system to manage data with different properties separately, improving both flexibility and space utilization efficiency.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If data are reordered in buffer, then data transfer order is improved, but buffer space is wasted waiting for earlier data

Engineering Contradiction:
Improvedata transfer order accuracyVSAvoidbuffer occupancy time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The buffer is divided into multiple lines, each handling specific data items. This segmentation allows parallel processing and transfer of data from different lines simultaneously, reducing the time buffer space is occupied while maintaining correct data transfer order through the structured organization of data across lines.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Data items are pre-assigned to specific buffer lines based on their transfer sequence requirements. This preliminary organization allows the system to prepare data for transfer in advance without wasting buffer space, as each data item knows its designated location and can be transferred immediately when ready.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If all data are stored in buffer temporarily, then data reordering is achieved, but buffer resource is wasted

Engineering Contradiction:
Improvedata sequence orderingVSAvoidbuffer resource efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The buffer is segmented into multiple specialized lines, each handling specific data items. This segmentation enables the system to achieve data reordering and sequence accuracy while improving resource efficiency by allowing parallel operations and reducing the need to store all data temporarily in a single large buffer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of storing all data items in the buffer simultaneously, the system uses multiple buffer lines to store only the necessary data items that need reordering, transferring others directly or in parallel. This partial action approach maintains data sequence ordering while improving overall buffer resource efficiency.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS7987408B2Data buffering method
Publication Date: 2011.07.26 VIA TECH INC
  • US7987408B2 patent drawing
  • US7987408B2 patent drawing
  • US7987408B2 patent drawing

AI summary

In a data processing and buffering method, at least one read cycles are asserted to obtain at least one data, respectively, wherein each of the data includes at least one sub data and each data is specified with an address pointer and an enable bit array. When a certain sub data is received, the corresponding bit of the enable bit array is enabled. The corresponding sub data of the enabled bit is indicated by the address pointer.