Data Communication Bus Address Sharing Through Clock Duty-Cycle Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data communication buses are limited in the number of peripheral devices they can connect due to the need for unique bus addresses, and mechanisms that allow shared addresses without buffers increase latency and cost.
Innovation Solution
A data communication bus controller modulates the duty cycle of a clock signal to indicate selection of peripheral devices sharing the same address, allowing multiple devices to communicate without buffers or additional buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffers are used to separate peripheral devices on the same bus address, then address conflicts are avoided, but device complexity and cost increase
Solution Approach 1:
The patent extracts the address conflict resolution function from the buffer hardware and implements it through software-based arbitration in the bus controller. The bus controller uses a priority scheme to determine which peripheral device gets bus access when multiple devices share the same address, eliminating the need for physical buffers while maintaining reliable address conflict avoidance.
Solution Approach 2:
The bus controller acts as an intermediary between peripheral devices with shared addresses. Instead of using buffers to physically separate devices, the bus controller mediates access by implementing arbitration logic that resolves conflicts through priority-based selection, allowing multiple devices to share the same address without additional hardware separation.
2Reliability
If buffers are used to separate peripheral devices on the same bus address, then address conflicts are avoided, but latency increases
Solution Approach 1:
The patent removes the buffer hardware that caused latency by extracting the conflict resolution function to the bus controller's arbitration mechanism. This eliminates the additional data path through buffers, allowing peripheral devices to communicate directly with reduced latency while maintaining reliable address conflict avoidance through software-based priority arbitration.
3Reliability
If unique bus addresses are assigned to each peripheral device, then data communication is reliable, but the number of connectable devices is limited
Solution Approach 1:
The patent implements multi-functionality by allowing a single bus address to serve multiple peripheral devices through shared access. The bus controller manages this shared address space using priority-based arbitration, enabling one address to be universally used by multiple devices at different times without compromising data communication reliability.
Solution Approach 2:
The patent resolves the address space limitation by adding a temporal dimension to address usage. Instead of requiring spatial separation through unique addresses, the system uses time-division through priority-based arbitration, allowing multiple devices to share addresses sequentially based on their priority levels, thus increasing the number of connectable devices.
4Adaptability or versatility
If additional buses are used to connect more peripheral devices, then device connectivity increases, but device complexity and cost increase
Solution Approach 1:
The patent makes the existing bus structure universal by enabling multiple peripheral devices to share the same physical address and bus resources. Through priority-based arbitration in the bus controller, the system allows one bus to serve multiple devices without requiring additional separate buses, reducing overall system complexity while maintaining high device connectivity.
Data Source
AI summary
A computer-implemented method for data communication bus address sharing can include selecting, by at least one processor, one of two or more peripheral devices sharing an address of a data communication bus. The method can additionally include modulating, by the at least one processor, a duty cycle of a clock signal transmitted over the data communication bus to the two or more peripheral devices, wherein the modulating causes a low period of the clock signal to satisfy a threshold condition for indicating selection of the selected one of the two or more peripheral devices. The method can also include performing, by the at least one processor using the address, data communication over the data communication bus with the selected one of the two or more peripheral devices. Various other methods, systems, and computer-readable media are also disclosed.