Data Bus Interface Channel Controller for Multi-Width Transaction Alignment
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Solution Overview
Problem
Designers face challenges in implementing effective communication between different portions of a system using data bus architectures, particularly due to complexities arising from varying bit formats and the need for advanced communication functions beyond the base protocol specifications, which complicates the design of interface circuitry.
Innovation Solution
A method and circuit for processing read transactions of multiple bit widths in a channel control queue of an N-bit data bus, where commands are stored in a first-in-first-out queue and transmitted in different formats based on bit width compatibility, with delayed transmission until previous transactions are complete if the formats differ, using a data bus interface channel controller circuit and translation circuits to manage transaction formats and buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If interface circuitry is designed to handle multiple bit formats and advanced communication functions, then communication versatility is improved, but device complexity increases
Solution Approach 1:
The interface circuitry is segmented into separate functional blocks: a transaction format identifier that detects the format of incoming transactions, and a transaction aligner that independently aligns transactions to the data bus width. This segmentation allows the system to handle multiple bit formats without requiring a monolithic complex interface design, as each component has a specific, simplified function.
Solution Approach 2:
The transaction aligner acts as an intermediary component between the transaction format identifier and the data bus. It receives transactions in various bit formats, aligns them to the appropriate width, and then passes them to the data bus interface. This intermediary approach enables format conversion without directly complicating the core interface circuitry.
2Reliability
If transaction format alignment is enforced before data bus transmission, then communication reliability is improved, but transmission time increases
Solution Approach 1:
The transaction format identification and alignment operations are performed in advance, before the actual data transmission on the bus. By identifying the transaction format and aligning it to the data bus width beforehand, the system ensures format consistency is established prior to transmission, preventing errors during the actual data transfer phase.
Solution Approach 2:
The transaction aligner automatically adjusts transactions to match the data bus width without requiring external intervention or complex control logic during transmission. The alignment process is self-contained within the aligner block, which autonomously handles format conversion based on the identified transaction type, reducing the need for additional control overhead during critical transmission windows.
Data Source
AI summary
A data bus interface channel controller circuit for an N-bit data bus is described. A FIFO command queue is coupled to receive and buffer one or more commands formatted for M-bit transactions. A FIFO data queue is coupled to receive and buffer N-bit formatted data packets. A first translation circuit is coupled to the FIFO command queue and configured to translate the each commands into a selected one of a plurality of transaction formats. A transmission control circuit is coupled and configured to receive and transmit commands removed from the FIFO command queue. The transmission control circuit is configured to track a number of outstanding transmitted commands and, in response to receiving a command having a transaction format different from the previously received command, delay transmission of commands on the N-bit data bus until the number of outstanding transmitted commands equals zero.