Data Bus Inversion Circuit for Semiconductor Memory Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in reducing power consumption and signal noise during data read operations, particularly due to large current flow and noise introduction in data output buffer circuits, which impede high-speed and reliable data transmission.
Innovation Solution
A data bus inversion circuit that selectively inverts or non-inverts input data signals based on bit logic states, utilizing comparison deciding and data converting units to generate inversion control signals, thereby optimizing power consumption and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a data output buffer circuit with a large channel width transistor is used to provide impedance isolation and facilitate high speed data access, then data transmission speed is improved, but power consumption and signal noise increase due to large current flow during swing operations
Solution Approach 1:
The patent applies data bus inversion by inverting the data signal before it reaches the output buffer circuit. This inversion technique reduces the number of swing operations (transitions between high and low levels) required, thereby reducing the current flow and power consumption in the output driver circuit while maintaining high-speed data transmission capability
2Speed
If a data output buffer circuit with a large channel width transistor is used to provide impedance isolation and facilitate high speed data access, then data transmission speed is improved, but signal noise increases due to large current flow during swing operations
Solution Approach 1:
By inverting the data signal in advance, the patent reduces the frequency of swing operations in the output buffer circuit. This reduction in switching activity directly decreases the generation of signal noise while preserving the high-speed transmission performance enabled by the large channel width transistor
3Ease of operation
If data is transmitted through multiple circuits (memory cell, bit line sense amplifier, input/output sense amplifier, data output buffer circuit), then data read operation is achieved, but power consumption and signal noise accumulate at each stage
Solution Approach 1:
The patent introduces data bus inversion at an early stage in the data path, which reduces the switching activity and associated power consumption in subsequent circuits including the output buffer. This single inversion operation propagates through the system to reduce cumulative power consumption and noise across multiple circuit stages
Data Source
AI summary
A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.