Data Bus Inversion Encoding for Memory Systems
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Solution Overview
Problem
Data buses in memory systems face issues with cross talk, simultaneous switching noise, and power consumption due to high-speed data transmission, necessitating efficient data encoding techniques like Data Bus Inversion (DBI) to reduce adverse effects and unnecessary power draw.
Innovation Solution
Implementing DBI in memory systems by separating logic and RAM ICs with a bus, where the logic system includes DBI encoding and decoding circuitry, and modified RAM ICs store DBI bits with encoded data, allowing for efficient data inversion and decoding to minimize transitions and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted at high speed across the data bus, then data transfer speed is improved, but cross talk and simultaneous switching noise increase
Solution Approach 1:
The patent applies parameter changes by modifying the data encoding parameters through Data Bus Inversion. The system changes the data representation from standard binary to inverted binary based on transition count thresholds, thereby reducing simultaneous switching noise and cross talk while maintaining high-speed data transfer capability.
2Speed
If data is transmitted at high speed, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The system changes the data transmission parameters by applying DBI encoding that reduces the number of transitions. By inverting data bits based on transition count thresholds (5 or more transitions trigger inversion), the system reduces dynamic power consumption while maintaining high-speed operation.
Solution Approach 2:
The patent implements periodic action through the cyclic application of DBI encoding and decoding. The encoder periodically assesses transition counts and applies inversion when necessary, creating a rhythmic pattern of encoding/decoding operations that reduces overall power consumption while maintaining continuous high-speed data transfer.
3Adaptability or versatility
If DBI encoding is implemented with an additional DBI bit channel, then data inversion capability is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by combining the DBI bit with the data bits on the same physical transmission channel. Instead of adding a separate dedicated channel for the DBI bit, the system multiplexes the DBI indication with the data signal itself, thereby reducing device complexity while maintaining data inversion capability.
Solution Approach 2:
The transmission channel is made universal by serving dual purposes: carrying both data bits and DBI indication bits. The same physical channel performs multiple functions (data transmission and inversion indication), thereby reducing the overall number of channels needed and simplifying the device architecture.
4Adaptability or versatility
If logic circuitry is integrated on the RAM IC, then functionality is improved, but RAM IC size and complexity increase
Solution Approach 1:
The patent applies segmentation by dividing the system into two functional modules: a logic integrated circuit that handles DBI encoding/decoding and control logic, and a simplified RAM IC that handles only data storage. This segmentation reduces the RAM IC area while maintaining full functionality through the separate logic circuit.
Solution Approach 2:
The patent extracts the DBI encoding and decoding circuitry from the RAM IC and places it in a separate logic integrated circuit. By taking out these logic functions, the RAM IC is simplified and its area is reduced, while the logic circuit independently handles the complex encoding/decoding operations.
Data Source
AI summary
Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM ICs and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state.