Data Bus Inversion for Intermediate Voltage Stability
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Solution Overview
Problem
In data communication systems, maintaining an intermediate voltage at a stable midpoint between high and low voltage nodes is challenging due to current imbalances caused by disparate bit transitions, leading to signal drift and noise, which complicates power management and signal integrity.
Innovation Solution
Implementing a non-intuitive use of Data Bus Inversion (DBI) and data swapping between channels to control bit transitions, selectively applying DBI and/or swapping data to maintain the intermediate voltage within a target range, thereby correcting current imbalances and reducing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted using multiple sub-channels in parallel, then throughput is increased, but current fluctuations and noise increase due to disparate bit transitions
Solution Approach 1:
The patent combines multiple data channels into a single aggregated data bus for transmission. By merging the channels, the system maintains high throughput while reducing the number of separate signal paths that could cause noise. The aggregation allows for coordinated control of bit transitions across what was previously separate channels, enabling the DBI technique to effectively manage overall transition counts and reduce noise.
Solution Approach 2:
The patent dynamically changes the inversion state parameter of data bits based on the current transition count. By monitoring the number of bit transitions and conditionally inverting data bits when transitions exceed a threshold, the system adapts the transmission parameters in real-time to minimize noise while maintaining throughput. This parameter change approach allows the system to respond to varying data patterns and keep transition counts within acceptable ranges.
2Object-affected harmful factors
If Data Bus Inversion (DBI) is applied to reduce bit transitions, then noise is reduced, but an additional signal line is required to signal inversion state
Solution Approach 1:
The most significant bit of the aggregated data bus serves dual purposes: it carries data information and simultaneously functions as an inversion indicator signal. When this bit transitions, it signals to the receiver that the remaining data bits should be interpreted as inverted. This eliminates the need for a separate DBI control line, as the data bus itself provides the inversion signaling function, thereby reducing overall system complexity while maintaining noise reduction benefits.
3Reliability
If intermediate voltage is maintained at midpoint between high and low voltage, then signal integrity is improved, but current imbalances cause voltage drift and instability
Solution Approach 1:
The system implements feedback by monitoring the actual intermediate voltage level and comparing it to the desired midpoint reference. Based on this comparison, the DBI technique is applied to adjust the bit transition patterns in a way that corrects voltage drift. When the intermediate voltage deviates from the midpoint, the system modifies transmission patterns to restore balance, creating a closed-loop control mechanism that maintains both signal integrity and voltage stability.
Solution Approach 2:
The patent introduces asymmetric treatment of data bits based on their position and the current voltage state. Rather than treating all bits uniformly, the system selectively inverts specific bits (particularly the most significant bit used for signaling) to create an asymmetric pattern that counteracts voltage drift. This asymmetric approach allows precise control over current distribution and intermediate voltage maintenance while preserving overall data integrity.
Data Source
AI summary
An intermediate voltage is maintained between a first voltage and a second voltage by conditionally or selectively performing data bus inversion (DBI) and/or data swap operations on a first and second transmit channel. The operations are performed to, in some instances, create a current imbalance between the first and second channel where the intermediate voltage drifts toward a target range or target value between the first voltage and second voltage in response to the created imbalance.