Data Bus Sense Amplifier Timing to Cut Overlap Current
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Solution Overview
Problem
Conventional two-stage data bus sense amplifier circuits experience increased current consumption due to overlapping activation timings of enable signals for the first and second sense amplifier blocks, leading to unnecessary operation of the first sense amplifier block during the sensing operation of the second sense amplifier block.
Innovation Solution
A sense amplifier control unit is introduced to synchronize the first enable signal with the second enable signal, inactivating the first enable signal when the second sense amplifier block starts its operation, using delay units to generate and control the enable signals in response to a column control pulse signal and feedback signals, ensuring the first sense amplifier block is inactivated during the second sense amplifier's sensing operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the first sense amplifier block operates independently with its own enable signal, then the sensing operation can be initiated early, but the current consumption increases due to overlapping operation with the second sense amplifier block
Solution Approach 1:
The first sense amplifier block is activated in advance with the first enable signal before the second sense amplifier block starts operation. This preliminary action allows the first block to perform initial sensing functions while the second block is still initializing, optimizing the timing sequence without causing overlapping operation that would increase current consumption
Solution Approach 2:
The enable signal generation incorporates feedback mechanisms where the second enable signal is delayed based on the activation timing of the first enable signal. This feedback loop ensures that the first sense amplifier block is deactivated before the second block fully operates, preventing simultaneous operation and reducing current consumption while maintaining optimal sensing performance
Data Source
AI summary
A data bus sense amplifier circuit can include a first sense amplifier block configured to provide first amplified signals by sensing inputted signals, a second sense amplifier block configured to provide second amplified signals by sensing the first amplified signals, and a sense amplifier control unit configured to provide first and second enable signals which control activations of the first and second sense amplifier blocks, respectively, wherein the sense amplifier control unit controls the first enable signal to be synchronized with the second enable signal so that the first enable signal is inactivated.