Data Bus Part Synchronization Using Data Stream Transitions
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Solution Overview
Problem
Existing data bus systems face challenges in synchronizing local clock generators across interconnected data bus parts without a central synchronization clock, often requiring separate synchronization lines and dealing with propagation delays and phase mismatches.
Innovation Solution
A data bus part with a synchronization unit that detects transitions in the downstream data stream to regulate the internal clock frequency and set a defined phasing, allowing clock generators to synchronize with adjacent higher-order data bus parts without a central clock, using detected transitions as synchronization information and adjusting the internal clock signal accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate synchronization line is used to transmit synchronization signals to all connected data bus parts, then synchronization reliability is improved, but device complexity and hardware requirements increase
Solution Approach 1:
The patent combines the synchronization function with the existing data transmission lines. The synchronization information is embedded within the data stream itself, eliminating the need for separate synchronization lines. This merging approach maintains synchronization reliability while reducing hardware complexity and the number of required connection lines.
Solution Approach 2:
The data transmission lines are made multi-functional by enabling them to carry both data information and synchronization information simultaneously. The downstream data stream serves dual purposes: transmitting actual data while also providing timing and synchronization references for the clock generator, thereby eliminating dedicated synchronization hardware.
2Measurement precision
If a central system clock is provided to synchronize all data bus parts, then synchronization precision is improved, but device complexity and propagation delays increase
Solution Approach 1:
The patent segments the synchronization function by providing each data bus part with its own local clock generator that operates autonomously. Instead of a single central clock, each node has an independent clock source that is individually synchronized using the downstream data stream, distributing the synchronization function across multiple independent units.
Solution Approach 2:
Instead of having a central clock generate synchronization signals that propagate outward to all nodes, the patent inverts the approach by having each node's clock generator synchronize itself using information derived from the downstream data stream received from higher-order parts. This eliminates the need for a central clock distribution system.
3Ease of manufacture
If local clock generators are used in each data bus part, then device independence and ease of manufacture are improved, but synchronization accuracy deteriorates due to clock drift
Solution Approach 1:
The patent implements a feedback mechanism where the downstream data stream provides continuous timing information back to the local clock generator. The clock generator uses this feedback to detect transitions in the data stream and automatically adjusts its frequency and phase to match the incoming stream, compensating for drift and maintaining synchronization accuracy.
Solution Approach 2:
Each data bus part performs self-synchronization using its own local clock generator and the downstream data stream it receives. The synchronization unit within each part automatically detects transitions and regulates its internal clock frequency without requiring external intervention or complex centralized control, enabling easy manufacturing while maintaining accuracy.
4Device complexity
If synchronization information is transmitted through data lines, then separate synchronization lines are eliminated, but propagation delays and phase mismatches occur
Solution Approach 1:
The patent applies preliminary action by having the synchronization unit detect transitions in the downstream data stream and use these detected transitions as direct timing references for the clock generator. This anticipatory approach allows the system to pre-compensate for propagation delays by aligning the clock phase with the actual arrival time of data transitions, eliminating the need for separate delay compensation mechanisms.
Data Source
AI summary
A data bus part with a data bus interface which has a downstream data bus input for receiving data from a higher-order data bus (1), and a clock generator for generating an internal clock signal for the data bus part, is described. The data bus part has a synchronization unit to synchronize the clock generator with the clock signal of the higher-order data bus part, wherein the synchronization unit is configured to detect transitions in the downstream data stream received at the downstream data input, to regulate the frequency of the internal clock signal depending on the detected transitions, and to set a defined phasing of the internal clock signal in relation to the detected transitions.