Data Bus Subscriber Synchronization for Deterministic Ring Bus Propagation

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Solution Overview

Problem

In automation systems, direct connection of automation devices to control units via parallel wiring is expensive and increases cabling effort with increasing automation, leading to high costs in design, installation, and maintenance. Existing bus systems help reduce these costs but can have non-deterministic propagation times due to varying processing times of data bus subscribers in ring buses.

Innovation Solution

A data bus subscriber with an input and output interface, processing component, and logic unit that synchronizes data processing and transmission, ensuring a constant delay to maintain deterministic propagation times by using delay elements and a validity signal to stabilize changes before transmitting data on a ring bus.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data bus subscribers process data at different speeds, then processing flexibility is improved, but propagation time becomes non-deterministic

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidpropagation time determinism
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing propagation time values in a table memory before data transmission occurs. Each data bus subscriber determines its processing time in advance and stores this information, allowing the master controller to calculate total propagation time deterministically without waiting for actual processing to complete. This resolves the contradiction by making processing time predictable while allowing subscribers to process data at their own speeds.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic action through cyclic data transmission rounds where data packets are transmitted in regular intervals around the ring bus. Each subscriber processes data during designated time slots in a repeating cycle, ensuring that propagation times are consistent and predictable across multiple transmission rounds. This periodic structure maintains determinism while allowing flexible processing within each cycle.

Inventive Principle:
Principle #19Periodic action

2Reliability

If parallel wiring is used to connect automation devices directly to control units, then control reliability is improved, but installation cost and complexity increase

Engineering Contradiction:
Improvecontrol reliabilityVSAvoidcabling complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the automation system into modular data bus subscribers that can be independently connected to the ring bus. Instead of requiring direct point-to-point wiring from each device to the control unit, the system segments connections into standardized bus interfaces. This reduces cabling complexity while maintaining reliability through the distributed architecture where each subscriber independently processes and forwards data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements universality by designing data bus subscribers with multi-functional capabilities. Each subscriber can act as both a data processor for its own automation devices and as a data forwarder to other subscribers. This universal interface design allows different automation devices to be connected through a common bus protocol, eliminating the need for dedicated wiring for each device-control unit pair while maintaining system reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Speed

If data is transmitted immediately after processing, then transmission speed is improved, but propagation time varies

Engineering Contradiction:
Improvetransmission speedVSAvoidpropagation time consistency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-determining propagation time values for each data bus subscriber before actual data transmission. The master controller queries each subscriber's processing time in advance and stores these values in a table. This allows the system to calculate the exact propagation time for each data packet around the ring, ensuring consistent timing while maintaining fast transmission speeds during actual data flow.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where data bus subscribers report their processing times back to the master controller. This feedback information is used to update propagation time tables and adjust transmission timing accordingly. The feedback loop ensures that transmission speeds remain high while propagation times stay consistent, as the system continuously adapts to actual processing performance of each subscriber.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11947475B2Synchronized processing of process data and delayed transmission
Publication Date: 2024.04.02 WAGO VERW GMBH
  • US11947475B2 patent drawing
  • US11947475B2 patent drawing
  • US11947475B2 patent drawing

AI summary

A data bus subscriber and a method for processing data, wherein the data bus subscriber can be connected to a local bus, particularly a ring bus, and the data bus subscriber has an input interface, which can be connected to the local bus, for receiving first local bus data, an output interface, which can be connected to the local bus, for transmitting second local bus data, a processing component for synchronous processing of the first local bus data and/or data stored in a memory and for output of at least one control signal, a logic unit, which is adapted in order to modify a quantity of received first local bus data based on the control signal in order to generate the second local bus data to be transmitted, wherein the logic unit is further adapted for synchronous, delayed transmitting of the second local bus data via the output interface.