Data Cache Module with Persistent Memory for Graph Computing

Solution Overview

Problem

Existing data storing systems face challenges in maintaining data consistency and reducing checkpoint committing overhead, especially in graph computing, due to insufficient cache space and redundant checkpoint operations, which increase memory access costs and system downtime.

Innovation Solution

A data storing system with a data cache module and persistent memory that includes a mapping data cache, counter cache, and metadata registers, which evicts least recently used mapping data and uses flag bits to manage storage regions for checkpoint and working data, ensuring data recovery and reducing checkpoint committing operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the mapping data cache is used to store mapping data for checkpoint and working data, then data consistency and data recovery capability are improved, but cache space is insufficient when handling large amounts of graph data, leading to frequent evictions and increased memory access costs

Engineering Contradiction:

Improvedata consistencyVSAvoidcache space

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent divides the persistent memory into multiple storage regions (first storage region for checkpoint data, second storage region for working data) and uses a segmented mapping data cache structure. This segmentation allows the system to manage different types of data separately, improving cache utilization and reducing the need for frequent evictions while maintaining data consistency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary actions by pre-establishing storage regions and mapping relationships before data processing. The mapping data cache stores mapping information in advance, and the system pre-configures the checkpoint mechanism with normal points. This preliminary setup reduces the need for frequent cache evictions and memory accesses during actual data processing.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If periodic checkpoint publishing is implemented to maintain crash consistency, then data recovery capability is improved, but checkpoint committing overhead increases, leading to increased memory access costs and system downtime

Engineering Contradiction:

Improvecrash consistencyVSAvoidcheckpoint committing overhead

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent implements preliminary actions by pre-establishing storage regions and mapping relationships before data processing. The mapping data cache stores mapping information in advance, and the system pre-configures the checkpoint mechanism with normal points. This preliminary setup reduces the need for frequent cache evictions and memory accesses during actual data processing.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent maintains the continuity of useful action by ensuring that checkpoint operations do not interrupt normal data processing flow. The system continuously updates the mapping data cache and counter cache, and checkpointing occurs seamlessly when storage regions need to be switched or when crash consistency is required, minimizing system downtime and maintaining productivity.

Inventive Principle:

Principle #20Continuity of useful action

3Reliability

If redundant checkpoint operations are performed to ensure data consistency, then data recovery capability is improved, but memory access costs increase and system performance deteriorates

Engineering Contradiction:

Improvedata recovery capabilityVSAvoidmemory access costs

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by treating different storage regions and data types differently. The first storage region is dedicated to checkpoint data while the second is for working data, allowing the system to optimize access patterns for each region. This localized organization reduces redundant memory accesses and improves overall system performance while maintaining data recovery capability.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent maintains the continuity of useful action by ensuring that checkpoint operations do not interrupt normal data processing flow. The system continuously updates the mapping data cache and counter cache, and checkpointing occurs seamlessly when storage regions need to be switched or when crash consistency is required, minimizing system downtime and maintaining productivity.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS12197330B2Data storing systems, data storing methods, and electronic devices

Publication Date: 2025.01.14 ZHEJIANG LAB

AI summary

The present disclosure provides a data storage system, including data cache module, data processing module, and a persistent memory. The data cache module includes an on-chip mapping data cache and an on-chip counter cache, where the mapping data cache is configured to cache mapping data, and when the free space of the mapping data cache is less than a preset threshold, the least recently used mapping data cache line will be evicted from the cache and written back to the persistent memory. The data processing module encrypts/decrypts persistent memory data by using their counters, and accesses the persistent memory blocks indicated by their corresponding mapping data. The persistent memory comprises the first and second storage regions for the latest checkpoint data and modified working data in the current checkpoint interval respectively.