Data Caching Method Using Cell Concatenation for Bus Utilization

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Solution Overview

Problem

In packet switched networks, the utilization of cache and bus resources is low due to inefficient caching methods, leading to suboptimal performance and potential packet loss during network congestion.

Innovation Solution

A data caching method and device that uses a First-In-First-Out (FIFO) queue to store and dequeue cells based on input and output port numbers, with cell concatenation and de-concatenation techniques to optimize resource utilization, where cells are dequeued when back pressure count values meet specific thresholds, and stored in registers with bit widths matching the bus width.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If variable-length cell switching is used, then cache resource utilization is improved, but bus resource utilization remains low

Engineering Contradiction:
Improvecache resource utilizationVSAvoidbus resource utilization
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments cells into fixed-length units that match the bus width, allowing efficient bus utilization while maintaining variable-length cell switching benefits. Cells are divided into multiple fixed-length segments for bus transmission, then reassembled at the destination.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of cell length from variable to fixed for bus transmission purposes. By converting variable-length cells into fixed-length segments that match the bus width, the system achieves both high cache utilization (through variable-length logical cells) and high bus utilization (through fixed-length physical segments).

Inventive Principle:
Principle #35Parameter changes

2Reliability

If cache space is increased to handle network congestion, then packet loss is reduced, but chip area and cost increase

Engineering Contradiction:
Improvepacket loss preventionVSAvoidcache space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent implements dynamic cache allocation where the cache space required is adjusted based on actual network conditions. The cache depth is dynamically determined by the product of link count, optical fiber length, and data rate, allowing the system to adapt cache resources to current traffic demands rather than over-provisioning for worst-case scenarios.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system uses feedback mechanisms to monitor network congestion levels and adjust caching strategies accordingly. By tracking the actual utilization patterns and congestion events, the system optimizes cache usage to prevent packet loss only when necessary, rather than maintaining maximum cache capacity continuously.

Inventive Principle:
Principle #23Feedback

3Speed

If data rate is increased from 12.5G to 25G, then transmission speed is improved, but cache capacity must be doubled to guarantee no forwarding loss

Engineering Contradiction:
Improvedata rateVSAvoidcache capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent makes cache capacity dynamically scalable based on data rate requirements. When data rate increases from 12.5G to 25G, the system automatically adjusts the number of cache units to maintain appropriate buffering capacity, rather than requiring a fixed doubling of cache resources. The dynamic adjustment is based on the relationship between link count, fiber length, and data rate.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3206123B1Data caching method and device, and storage medium
Publication Date: 2020.04.29 SANECHIPS TECH CO LTD
  • EP3206123B1 patent drawingFigure 1~3
  • EP3206123B1 patent drawingFigure 4~5
  • EP3206123B1 patent drawingFigure 6~7

AI summary

Disclosed is a data caching method, comprising: according to an input port number of a cell, storing the cell in a corresponding first-in first-out queue; determining that a cell to be dequeued can be dequeued in the current Kth cycle, scheduling for the cell to be dequeued to be dequeued, acquiring the actual value of the number of splicing units occupied by the cell to be dequeued, and storing the cell to be dequeued in a register the same number of bits wide as a bus in a cell splicing manner, wherein determining that the cell to be dequeued can be dequeued is conducted in accordance with the fact that a first back pressure count value of the (K-1)th cycle is less than or equal to a first preset threshold value, and the first back pressure count value of the (K-1)th cycle is obtained in accordance with an estimated value of the number of the splicing units occupied when the previous cell to be dequeued is dequeued, the number of splicing units capable of being transmitted by the bus in each cycle, and a first back pressure count value of the (K-2)th cycle. Also disclosed at the same time are a data caching device and a storage medium.