Data Capture Device Read Preamble Timing Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-speed data transfer scenarios, existing memory systems face challenges in accurately capturing data due to shrinking clock periods and relatively constant data valid and hold times, leading to difficulties in determining the optimal data capture point, especially in serial memory interfaces like SPI protocols.
Innovation Solution
The implementation of a data capturing device that includes a DLL component, data sampling component, comparison component, and valid clock calculation component, which uses a read preamble with a training pattern to align the capture point with the memory system data, allowing for reliable data capture even at higher clock frequencies by determining the valid clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency is increased to improve data throughput, then productivity is improved, but measurement precision of data capture timing deteriorates
Solution Approach 1:
The patent applies preliminary action by inserting a read preamble with training pattern before the actual data transfer. This training pattern allows the data capturing device to预先 determine the optimal capture point by comparing the training pattern with expected values, establishing timing alignment before high-speed data arrival. This resolves the contradiction by preparing the capture timing in advance, enabling accurate data capture even at increased clock frequencies.
2Speed
If clock period is shrunk to increase data transfer speed, then speed is improved, but reliability of data capture deteriorates
Solution Approach 1:
The patent implements feedback by comparing the captured training pattern with the expected training pattern and using this comparison to determine the valid clock signal. The data capturing device adjusts its capture timing based on the feedback from the training pattern comparison, ensuring reliable data capture. This feedback mechanism allows the system to adapt to timing variations and maintain capture reliability even when clock periods are shrunk to increase transfer speed.
3Reliability
If data valid time is extended to improve capture reliability, then reliability is improved, but loss of time increases
Solution Approach 1:
By performing the timing calibration using the training pattern in advance, the system establishes the optimal capture point before actual data transfer begins. This preliminary timing determination eliminates the need for extended data valid times during actual data transfer, as the capture timing is already optimized. The result is improved capture reliability without sacrificing read timing margins or increasing time loss.
Data Source
AI summary
A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to.