Data Reading Writing Circuit Clock Synchronization
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Solution Overview
Problem
Conventional data reading/writing technologies face high clock synchronization complexity due to differing time deviations between clock signals for different storage modules, requiring frequent adjustments of synchronization parameters when switching operations among storage modules.
Innovation Solution
Implementing a data reading/writing circuit with separate synchronization parameters for each storage module, using a first synchronization parameter for initial synchronization and a second synchronization parameter for superposition synchronization, reducing the need for parameter modifications during operation switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single synchronization parameter is used for multiple storage modules, then the device complexity is reduced, but the manufacturing precision of clock synchronization deteriorates due to differing time deviations between storage modules
Solution Approach 1:
The patent divides the synchronization parameter management into segments: a first synchronization parameter stored in the controller and a second synchronization parameter stored in each storage module. This segmentation allows each module to have its own customized synchronization parameters, achieving precise clock synchronization for each storage module while maintaining manageable complexity through the structured division of synchronization responsibilities.
2Manufacturing precision
If synchronization parameters are frequently adjusted when switching operations among storage modules, then the clock synchronization accuracy is maintained, but the loss of time increases due to frequent parameter modifications
Solution Approach 1:
The patent implements preliminary action by pre-storing the second synchronization parameter in each storage module before operations are switched. When a storage module becomes the active operation object, its pre-stored synchronization parameter is immediately applied without requiring real-time adjustment. This eliminates the time loss associated with frequent parameter modifications while maintaining synchronization accuracy.
3Manufacturing precision
If separate synchronization parameters are implemented for each storage module, then the manufacturing precision of clock synchronization is improved, but the device complexity increases due to multiple parameters and storage locations
Solution Approach 1:
The patent applies local quality by allowing each storage module to have its own second synchronization parameter tailored to its specific time deviation characteristics. This enables each module to operate with optimized synchronization parameters for its local conditions, achieving high precision clock synchronization for each module while the overall system complexity is managed through the clear separation of parameter storage and usage responsibilities.
Data Source
AI summary
A data reading/writing circuit includes a controller and a memory. The memory is configured to decode an instruction based on a first clock signal from the controller and to sample data based on a second clock signal from the controller. The memory includes first and second storage modules, and a mode register that stores a second synchronization parameter, and a second delay circuit is disposed in the second storage module. In reading/writing data on the first storage module, the controller is configured to synchronize the first and second clock signals using a first synchronization parameter. In reading/writing data on the second storage module, the controller is configured to perform first synchronization on the first and second clock signals using the first synchronization parameter, and the memory is configured to perform second synchronization on the first and second clock signals using the second delay circuit and the second synchronization parameter.