Data Clock Delay Compensation for Accurate UHS-I Bus Sampling
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Solution Overview
Problem
The Secure Digital (SD) standard's Ultra High Speed (UHS-I) bus design faces challenges in data transfer due to varying loop delays and peripheral clock frequencies, leading to incorrect data reading by hosts as data is often provided on or near the transition of the peripheral clock.
Innovation Solution
A delay compensation circuit is implemented in the controller to generate a delayed data clock, adjusting its phase relative to the peripheral clock based on feedback from the data signal, ensuring data is transmitted at a predetermined edge of the clock cycle, thereby avoiding incorrect reading by the host.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is provided on or near the transition of the peripheral clock to maximize transfer speed, then data transfer rate is improved, but data reading accuracy deteriorates due to incorrect sampling by the host
Solution Approach 1:
The patent applies preliminary action by delaying the data clock relative to the peripheral clock before data transmission occurs. This pre-adjustment ensures that data is provided at an optimal time that allows the host to sample it correctly, preventing sampling errors while maintaining high transfer rates. The delay is calculated in advance based on the loop delay characteristics of the system.
Solution Approach 2:
The patent implements feedback by measuring the actual loop delay in the system and using this information to adjust the data clock delay. The system monitors the timing relationship between data provision and host sampling, then dynamically adjusts the delay to optimize both transfer speed and reading accuracy based on real-time conditions.
2Reliability
If loop delay is reduced to improve data timing, then data transfer reliability is improved, but device complexity increases due to additional delay compensation circuits
Solution Approach 1:
The patent introduces an intermediary element - a delay compensation circuit - that mediates between the data source and the host interface. This circuit acts as a buffer that can be dynamically adjusted to compensate for loop delay variations, simplifying the overall system design compared to redesigning the entire data path for each timing condition.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the delay parameter of the data clock based on measured loop delay conditions. Instead of fixing the architecture to handle all timing scenarios, the system changes the timing parameter adaptively, maintaining reliability while keeping the hardware design relatively simple.
3Productivity
If peripheral clock frequency is increased to improve transfer rate, then productivity is improved, but data sampling accuracy worsens due to reduced timing margin
Solution Approach 1:
The patent applies preliminary action by pre-calculating and applying an appropriate delay to the data clock based on the peripheral clock frequency before data transmission begins. This ensures that even at high frequencies where timing margins are reduced, the data is provided at the optimal moment for sampling, maintaining accuracy while enabling high-speed operation.
Solution Approach 2:
The patent implements dynamics by making the data clock delay adjustable and adaptive to different peripheral clock frequencies. Rather than using a fixed delay, the system dynamically adjusts the delay parameter based on the operating conditions, allowing optimal performance across a range of frequencies from low to high speeds.
Data Source
AI summary
Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is detected on the bus. A delayed data clock having the selected delay relative to the peripheral clock may be generated. Requested data may be provided on the bus in response to an edge of the delayed data clock.