Semiconductor Data-Clock Extension for Lower Current Consumption
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Solution Overview
Problem
Existing semiconductor systems face challenges in maintaining clock synchronization operations during high-speed data transfer, leading to increased current consumption and inefficiencies in data handling.
Innovation Solution
The semiconductor system includes a driving signal generation circuit and a sync enable signal generation circuit that manage pull-up and pull-down signals to extend clock synchronization operations, allowing for data clock extension before normal operations are completed, thereby reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock synchronization operation is extended during high-speed data transfer, then data transfer rate is improved, but current consumption increases
Solution Approach 1:
The patent applies periodic action by using multi-phase clocks to periodically enable data clock reception during specific intervals (e.g., during write or read operations) rather than continuously. The sync enable signal periodically activates the data clock input circuit only when needed for synchronization, reducing overall current consumption while maintaining high-speed data transfer capability when required.
Solution Approach 2:
The patent implements dynamics by making the data clock reception capability dynamic rather than static. The input circuit is dynamically enabled or disabled based on the state of sync enable signals, allowing the system to adapt its operational state to match actual data transfer needs, thereby reducing energy consumption during idle periods while maintaining high performance during active transfer.
2Reliability
If data clock reception is continuously enabled, then clock synchronization is maintained, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by proactively managing the enablement of data clock reception based on predicted or scheduled operation intervals. The sync enable signal is generated in advance to enable data clock reception only during periods when write or read operations are expected to occur, rather than maintaining continuous reception capability. This ensures synchronization is maintained when needed while avoiding unnecessary power consumption during idle periods.
3Productivity
If multi-phase clock is used for high-speed data transfer, then data bandwidth is improved, but system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the clock signal into multiple phases (e.g., first through fourth internal clocks with different phases) to handle different aspects of data transfer simultaneously. Each phase can be used for specific operations such as data input, output, or synchronization, allowing high bandwidth utilization while organizing the complexity into manageable, functionally-separated segments rather than a monolithic complex system.
Data Source
AI summary
A semiconductor device includes a driving signal generation circuit configured to generate a pull-up driving signal that is enabled when a data clock input control signal is input during a normal operation, configured to generate a pull-down driving signal that is enabled when any one of a write signal and a read signal is input, and configured to generate the pull-down driving signal that is enabled after a set interval when a synchronization signal is input, and a sync enable signal generation circuit configured to generate a sync enable signal for receiving a data clock from a time at which the pull-up driving signal is enabled to a time at which the pull-down driving signal is enabled.