Data Clock Leading Bus Clock with Skew Correction
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Solution Overview
Problem
In shared bus systems, synchronization of internal bus clocks between agents is crucial for reliable data transfer, but inherent characteristics can cause one agent to drive data later than others, leading to timing issues as bus frequencies increase, potentially resulting in data not being latched in time by destination agents.
Innovation Solution
A system that employs a data clock designed to lead the bus clock, combined with a skew corrector that ensures data is passed only when both clocks are in a predetermined state, mitigating racing and delay by using a master-slave flip flop structure with NOR gates to synchronize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bus frequency is increased to improve data transfer speed, then productivity is improved, but reliability deteriorates due to timing issues and data not reaching destination in time
Solution Approach 1:
The data clock is advanced relative to the bus clock to perform the data driving action earlier in the cycle. This preliminary action ensures that data is placed on the bus before the bus clock edge, providing a time margin that maintains reliability even at higher frequencies where timing margins are compressed.
2Reliability
If data clock is advanced to lead the bus clock and improve timing margin, then reliability is improved, but device complexity increases due to skew correction requirements
Solution Approach 1:
A skew correction circuit is introduced as an intermediary component that mediates between the data clock and bus clock signals. This circuit monitors the relative phases of the two clocks and dynamically adjusts the data clock phase to maintain the proper leading relationship, thereby managing the complexity in a controlled manner while ensuring synchronization reliability.
3Reliability
If skew correction is implemented to prevent racing conditions, then reliability is improved, but loss of time occurs due to additional synchronization overhead
Solution Approach 1:
The system dynamically changes the phase parameter of the data clock relative to the bus clock. By adjusting the phase relationship rather than adding substantial correction logic, the system prevents racing conditions and ensures reliable data capture while minimizing the time overhead associated with skew correction.
Data Source
AI summary
Systems and methods for driving data over a data bus are disclosed. One embodiment of a system may comprise a bus clock signal that is a copy of a system clock signal that controls the timing associated with transferring data over the bus, a data clock signal that is designed to lead the system clock by a portion of a clock cycle to drive data over the bus ahead of the bus clock signal, an output latch device that drives data over the data bus in response to an edge of the data clock signal and a skew corrector that mitigates racing of data over the data bus in the event that the data clock lags the bus clock.