Clock-Gated Flip-Flop Using Data Comparison to Cut Switching Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing edge-triggered flip-flops in digital circuits consume significant power due to dynamic power consumption from clock flipping and data transmission, which is not efficiently optimized in standard cell libraries.
Innovation Solution
A flip-flop unit with a clock gating circuit that enables clock flipping only during clock cycles where input data is flipped, and maintains the clock signal at a predetermined level when the input data remains unchanged, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock signal continuously flips in edge-triggered flip-flop, then data transmission function is maintained, but dynamic power consumption increases significantly
Solution Approach 1:
The patent extracts the clock gating control function from the main flip-flop circuit by adding a separate clock gating circuit. This control circuit compares input data with output data and generates a clock control signal to selectively enable or disable clock signal transmission, thereby separating the data transmission function from continuous clock flipping and reducing dynamic power consumption
Solution Approach 2:
The patent implements dynamic clock gating control where the clock signal transmission is dynamically adjusted based on whether data has changed. The clock gating circuit dynamically generates control signals to enable clock flipping only when input data differs from output data, making the clocking behavior adaptive rather than static, thus reducing unnecessary power consumption while maintaining data transmission reliability
2Loss of energy
If data signal flips frequently in edge-triggered flip-flop, then information is transmitted, but additional data power consumption occurs in subsequent-stage combinational logic units
Solution Approach 1:
The patent performs preliminary comparison of input data with output data before the clock signal is generated. The clock gating control circuit预先 (in advance) determines whether data has changed and only enables clock signal transmission when necessary, preventing unnecessary data transmission and subsequent logic unit operations, thereby reducing data power consumption while maintaining information transmission productivity
Data Source
AI summary
A flip-flop with clock gating based on data comparison is disclosed. The flip-flop unit includes an edge-triggered flip-flop and a clock gating circuit. The clock gating circuit enables or disables a first clock signal to generate a second clock signal according to a data comparison result of input data and output data. The second clock signal provides a triggering edge of the edge-triggered flip-flop. The clock gating circuit copies the first clock signal as the second clock signal in a clock cycle during which the input data is flipped, and maintains the second clock signal at a predetermined level in clock cycles during which the input data remains unchanged. The flip-flop unit enables the clock flip of the edge-triggered flip-flop only in a clock cycle during which the input data is flipped, thereby improving the circuit performance and reducing the power consumption.