Data Delay Cell Gain Error Compensation in Write Preamplifier
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Solution Overview
Problem
The existing methods for controlling the rise time of the write current in a hard disk drive are affected by error currents introduced by current mirror circuitry in the bias circuit, leading to inaccuracies in the delay of the write current, which can result in errors between 15% and 35% of the target current.
Innovation Solution
A data delay circuit with compensation circuitry that includes a replica of the charge current source, a replica of the reference current source, and a gain cell, where the combined replica currents are fed back through the gain cell to reduce the gain error, and optionally incorporates a proportional-to-absolute-temperature current source for temperature compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If current mirror circuitry is used in the bias circuit to control the delay, then the delay can be programmably controlled, but error current is introduced having a magnitude between 15% and 35% of the target current
Solution Approach 1:
The patent introduces feedback circuitry that senses the error current generated by the current mirror and feeds it back to compensate for the delay error. The feedback mechanism adjusts the delay cell operation based on the detected error, thereby reducing the 15-35% error current impact and improving delay accuracy while maintaining programmable control.
Solution Approach 2:
The patent employs an intermediary compensation circuit that acts as a mediator between the current mirror bias circuit and the delay cell. This intermediary circuit generates correction signals that offset the error current effects, allowing the system to maintain both programmability and accuracy without directly modifying the original current mirror operation.
2Device complexity
If the gain error in the data delay cell and bias circuit is not compensated, then the circuit operation is simple, but the error in write current rise time can be as high as 15% to 35%
Solution Approach 1:
The patent implements feedback mechanisms that continuously monitor the gain error in the delay cell and bias circuit, then automatically adjust operating parameters to compensate. This feedback approach maintains circuit reliability by correcting accuracy errors while adding minimal complexity compared to complete redesign.
Solution Approach 2:
The compensation circuitry is designed to be self-regulating, automatically detecting and correcting its own gain errors without requiring external calibration or complex control systems. The circuit serves itself by generating internal correction signals that maintain write current accuracy within acceptable tolerances.
Data Source
AI summary
A data delay circuit, for delaying a portion of a data signal for application to a write head of a hard disk drive, includes a data delay cell including two inverters and a charge current source for charging at least one of the inverters, and a bias circuit for programming delay of the data delay cell. The bias circuit is in current-mirroring relationship with the charge current source and includes a current-based digital-to-analog converter (DAC) for programmably selecting the delay of the data delay cell, and a reference current source for the DAC. The data delay cell and the bias circuit are subject to gain error, and the data delay circuit further includes compensation circuitry for reducing the effect of the gain error. The compensation circuitry may include replica charge current and reference current sources that are fed back through a gain cell.