Register-Based Data Delay Circuit With Lower Power Switching
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Solution Overview
Problem
Existing data delay circuits with multiple stages of registers suffer from high power consumption due to the need for data storage and read operations on each level, especially with larger data bit widths or register quantities.
Innovation Solution
A data delay method and circuit that utilizes N independent first registers, where data is stored in a target register in an Mth clock cycle and output in the Mth cycle as data from the (M−N)th cycle, reducing operations to one register per cycle, and incorporates counters and selection elements to manage register access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple stages of registers are used for data delay, then the data delay function is achieved, but the power consumption increases significantly
Solution Approach 1:
The patent divides the data delay function into N independent first registers, where each register handles a portion of the data bits. Instead of sequentially accessing each register stage for every bit, the system segments the data width and allows parallel access to the necessary registers, reducing the total number of read/write operations and thereby lowering power consumption while maintaining the delay function.
Solution Approach 2:
The patent transitions from a time-sequential access model (where data passes through N stages sequentially) to a spatial-parallel access model (where N independent registers can be accessed simultaneously or in fewer cycles). By changing the dimension of access from temporal to spatial, the system achieves the same delay function with fewer operations, reducing power consumption.
2Quantity of substance
If larger data bit width is used, then the data processing capability is improved, but the power consumption overhead increases
Solution Approach 1:
The patent segments the large data width into N independent first registers, each handling a portion of the bits. This segmentation allows the system to process wide data in parallel across multiple registers rather than sequentially through many stages, reducing the number of clock cycles and operations required, thereby lowering power consumption overhead while maintaining large data bit width capability.
3Loss of time
If larger quantity of register stages is used, then the data delay duration is increased, but the power consumption increases
Solution Approach 1:
The patent introduces dynamic control mechanisms (counters and selection elements) that adaptively manage which registers are accessed and when. Instead of fixed sequential access through all N stages, the system dynamically determines the minimum necessary register accesses based on the current clock cycle and data requirements, reducing unnecessary operations and power consumption while maintaining the required delay duration.
Data Source
AI summary
A data delay method, apparatus, and circuit, an electronic device, and a readable storage medium, are provided. The data delay method is performed by an electronic device. The electronic device includes a data delay circuit, the data delay circuit includes N independent first registers, and the method includes: storing first data in a target register in an Mth clock cycle, where the target register is an Lth first register of the N first registers; and when M is greater than N, obtaining, in the Mth clock cycle, second data output by the target register, where the second data is data stored in the target register in an (M−N)th clock cycle.