Data Detection Circuit for HSSI Event Capture
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Solution Overview
Problem
High-speed serial interface (HSSI) protocols face challenges in accurately monitoring data communications and detecting specific events due to limitations in existing data detection and event capture methods, which result in inefficiencies and inaccuracies in time-aware applications.
Innovation Solution
A data detection and event capture circuit is developed, incorporating data comparator logic, any pattern detection logic, and sequence detection logic to generate pattern and sequence detected signals from a parallel data bus, enabling precise monitoring and event signaling in HSSI transmitters and receivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing data detection and event capture methods are used in HSSI protocols, then basic data monitoring is achieved, but detection accuracy and event capture precision are insufficient
Solution Approach 1:
The detection circuit is segmented into three independent logic modules: data comparator logic for pattern matching, any pattern detection logic for parallel pattern evaluation, and sequence detection logic for temporal sequence verification. This segmentation allows each module to specialize in specific detection tasks, improving overall detection accuracy while enabling modular design that manages complexity through functional decomposition.
Solution Approach 2:
The circuit employs dynamic configuration capabilities where the detection patterns and sequences can be programmatically set and modified. The logic circuits adapt their detection criteria based on configurable parameters, allowing the system to dynamically adjust to different detection requirements without hardware reconfiguration, thus improving precision without permanent complexity increase.
2Reliability
If multiple detection logic circuits are implemented to improve detection accuracy, then event capture precision improves, but circuit complexity and resource usage increase
Solution Approach 1:
Multiple detection functions are merged into a unified detection circuit architecture that processes data through a pipeline of logic stages. The data comparator, any pattern detector, and sequence detector are combined in a coordinated system that shares common data paths and control mechanisms, achieving high detection reliability while avoiding the complexity of completely separate independent circuits.
Solution Approach 2:
The detection circuit is designed with universal logic structures that can perform multiple detection functions through configurable parameters. The same hardware infrastructure supports various detection patterns and sequences by reconfiguring the logic operations, thereby improving reliability across different detection scenarios without proportionally increasing circuit complexity for each specific function.
3Measurement precision
If complex pattern and sequence detection logic is applied, then detection precision is improved, but processing latency increases
Solution Approach 1:
The data comparator logic performs preliminary pattern matching operations on incoming data words before passing results to subsequent detection stages. By pre-evaluating basic pattern criteria in the first stage, the circuit reduces the processing burden on later stages, enabling precise multi-stage detection while minimizing overall latency through early filtering and preparation.
Solution Approach 2:
The detection circuit operates continuously with pipelined processing where multiple detection stages work simultaneously on different data elements. The any pattern detection and sequence detection logic operate in parallel where applicable, maintaining continuous detection flow without idle periods, thus achieving high precision detection with reduced effective latency through uninterrupted processing.
Data Source
AI summary
One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment relates to a method of data detection and event capture. Another embodiment relates to an integrated circuit having a first data detection and event capture circuit in a receiver circuit and a second data detection and event capture circuit in a transmitter circuit. Other embodiments and features are also disclosed.