Data-Driven Internal Clock Circuit Without External Clock Locking
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Solution Overview
Problem
Conventional internal clock generating circuits require an extra signal line and locking time for external clock signals, complicating their structure and reducing operating speed.
Innovation Solution
An internal clock generating circuit that uses a transition detecting block to generate a data transition information signal, allowing the internal clock signal to be generated based on the data signal without an external clock, simplifying the circuit structure and eliminating the need for extra locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional internal clock generating circuits use PLL or DLL to generate internal clock signal from external clock signal, then the internal clock signal can be generated with stable frequency, but an extra signal line is required which complicates the circuit structure
Solution Approach 1:
The invention extracts and eliminates the external clock signal input requirement by generating the internal clock signal directly from the data signal transitions. The transition detecting block monitors data signal edges and generates clock transitions accordingly, removing the need for separate external clock signal lines and simplifying the overall circuit structure while maintaining reliable clock generation.
Solution Approach 2:
The data signal serves multiple functions: it carries information data and simultaneously provides the timing reference for internal clock generation. By detecting transitions in the data signal, the circuit generates internal clock signals without requiring dedicated external clock inputs, making the data signal universally serve both data transmission and clock synchronization purposes.
2Reliability
If conventional internal clock generating circuits use PLL or DLL to lock external clock signal, then stable internal clock signal is achieved, but extra locking time is required which reduces operating speed
Solution Approach 1:
The circuit performs preliminary detection of data signal transitions and immediately generates corresponding internal clock transitions without requiring a locking period. The transition detecting block is continuously monitoring data signal edges and can generate clock signals instantaneously upon detecting transitions, eliminating the time-consuming locking process required by conventional PLL or DLL circuits.
Solution Approach 2:
The data signal itself serves as the reference for generating the internal clock signal, eliminating the need for external clock signals and the associated locking mechanism. The circuit uses its own data input to generate timing signals, achieving immediate operation without the delay of external synchronization and locking procedures.
3Reliability
If extra signal line is added for external clock signal input, then internal clock can be generated using PLL or DLL, but the constitution of internal clock generating circuit becomes more complicated
Solution Approach 1:
The invention removes the external clock signal input line entirely by generating internal clock signals from data signal transitions. The transition detecting block monitors data edges and generates clock transitions directly, extracting the timing information from the data signal itself and eliminating the need for separate external clock signal paths and associated circuitry.
Solution Approach 2:
The invention merges the data signal input function with the clock reference function. The same data signal line that carries information also provides the timing reference for internal clock generation by detecting its transitions. This consolidation eliminates the need for separate external clock signal lines and simplifies the circuit constitution by combining multiple functions into a single signal path.
Data Source
AI summary
An internal clock generating circuit and a method for generating an internal clock signal are disclosed. The internal clock generating circuit includes a transition detecting block for detecting transitions in a data signal and generating data transition information, and an internal clock generating block for generating and storing a period digital data while detecting the unit period of the data signal in a period confirming mode. In the internal clock generating circuit, the internal clock signal can be generated without the external clock signal, so that the internal clock generating circuit can be implemented with a simple constitution. Additionally, an extra locking time is not required for locking the extra clock signal, so that the operating speed of the internal clock generating circuit is improved. The internal clock signal is dependent on the data signal, so that it is easy to control the set-up and hold for data.