Data-Driven Logic Verification Chip Architecture
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Solution Overview
Problem
Current chip verification technologies, such as cycle-based simulators and FPGA-based systems, are inefficient due to software overhead, high costs, and lack of scalability, especially when dealing with complex logic designs, as they do not effectively utilize data-driven execution and are not programmable or commercially available.
Innovation Solution
A data-driven logic verification chip architecture with a plurality of logic processors, a code generator for converting net-lists into data-driven logic programs, and an array simulation unit for efficient resource allocation and communication, enabling scalable and efficient logic simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cycle-based simulators are used for logic verification, then verification capability is provided, but software overhead and slow inter-workstation communication make them inefficient for larger verification targets
Solution Approach 1:
The patent replaces software-based cycle simulation with a hardware accelerator that uses data-driven execution architecture. The hardware system directly implements logic verification functions without software overhead, achieving significant performance improvement for large verification targets.
Solution Approach 2:
The patent introduces a hardware accelerator as an intermediary between the verification target and the user. This accelerator handles the computationally intensive simulation tasks, allowing the main system to focus on higher-level verification coordination and reducing overall software complexity.
2Adaptability or versatility
If FPGA-based verification systems are used, then programmability is improved, but construction cost and synthesis time increase significantly with target logic complexity
Solution Approach 1:
The patent changes the fundamental execution parameter from cycle-based software simulation to data-driven hardware execution. This parameter change enables the system to handle complex logic verification without the synthesis time penalties associated with FPGA configuration, while maintaining programmability through configurable hardware architecture.
3Ease of manufacture
If PC cluster is used for simulation, then cost is reduced, but performance is hindered by poor cache locality, inefficient communication, and OS overhead
Solution Approach 1:
The patent replaces the software-based PC cluster approach with a dedicated hardware accelerator. This hardware system eliminates OS overhead and achieves superior cache locality by design, while maintaining cost-effectiveness through specialized hardware implementation rather than relying on expensive general-purpose computing clusters.
4Productivity
If dedicated ASIC simulation machines are used, then simulation performance is accelerated, but development cost and lack of programmability increase
Solution Approach 1:
The patent creates a dynamic hardware accelerator that can be reconfigured for different verification tasks. Unlike fixed dedicated ASICs, this system allows flexible adaptation to various logic verification scenarios while maintaining high performance, thereby reducing development cost through reuse and versatility.
Data Source
AI summary
An apparatus and method may be used for compiling a hardware logic design into data-driven logic programs to be executed on a data-driven chip. The apparatus may include storage with a library for defining a net-list synthesized by a synthesis tool. The apparatus may also include a data-driven logic verification chip comprising a plurality of logic processors. The apparatus may further include a code generator for adopting heuristics to convert the net-list into data driven logic programs and for allocating hardware resources to balance computing and storage loads across the plurality of logic processors of the verification chip.