Data Driver RC Delay Compensation via Staggered Amplifier Timing
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Solution Overview
Problem
In liquid crystal display (LCD) apparatuses, the resistive-capacitive (RC) delay in gate lines leads to varying charging rates of pixels, affecting display quality due to differences in signal timing across the panel.
Innovation Solution
The data driver employs a configuration with multiple amplifiers and switches that control data voltage output timing based on enable signals, ensuring that data voltages are output at specific times during a horizontal duration to compensate for RC delay, thereby reducing distortion across the display panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data voltages are output simultaneously from all amplifiers, then the circuit operation is simple, but RC delay causes varying charging rates and display quality degradation
Solution Approach 1:
The patent applies preliminary action by controlling amplifiers to output data voltages at different predetermined times based on their position. The timing controller generates enable signals that activate amplifiers in sequence, with earlier amplifiers (closer to gate driver) outputting earlier and later amplifiers outputting later, compensating for RC delay effects before they degrade display quality.
Solution Approach 2:
The patent segments the data voltage output operation by dividing amplifiers into different groups that operate at different times. Each amplifier is controlled independently by timing signals to output data voltages during specific time windows, creating a segmented temporal operation pattern that compensates for spatial RC delay variations.
2Manufacturing precision
If amplifiers output data voltages at different times to compensate for RC delay, then display quality improves, but the timing control complexity increases
Solution Approach 1:
The patent implements feedback by using the position information of each amplifier as input to the timing controller, which then generates appropriate enable signals. The timing controller receives amplifier position data and automatically calculates the required timing offsets, creating a feedback loop that automatically compensates for RC delay without requiring manual timing adjustment.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the output timing parameter of each amplifier based on its position. The enable signals modify the temporal parameter (output time) of each amplifier, transforming a static simultaneous output system into a dynamic time-varying system that compensates for RC delay.
3Productivity
If all amplifiers operate simultaneously, then the horizontal duration utilization is low, but the circuit design is simpler
Solution Approach 1:
The patent applies continuity of useful action by overlapping the output time windows of different amplifiers. Instead of sequential operation with gaps, the enable signals are designed so that amplifier output periods overlap, ensuring continuous data voltage supply throughout the horizontal duration and maximizing productivity without requiring complex sequential control.
Data Source
AI summary
A data driver includes an N-th amplifier including first and second input nodes and a first output node and configured to output an N-th data voltage to an N-th data line, the first input node receiving the N-th data voltage from an N-th node, the second input node being connected to the first output node, a first switch connected between the N-th node and the first input node, and a second switch connected between the first input node and the second input node.