Data Driver Circuit Deskew Buffer for Clock Data Skew
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Solution Overview
Problem
As display devices evolve towards higher resolution, the increased driving frequency and number of output channels lead to a skew problem between clock and data, limiting frequency enhancement due to longer data paths, resulting in data sampling errors.
Innovation Solution
A data driver circuit is designed with a bi-directional deskew buffer that synchronizes clock and data signals across channels, using clock and data buffers to correct skew between adjacent channel blocks, enabling higher frequencies and channel counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of output channels is increased to achieve high resolution, then the driving capability is improved, but the data path length increases causing skew between clock and data
Solution Approach 1:
The data driver circuit is divided into multiple channel blocks, with bi-directional deskew buffer parts disposed between adjacent channel blocks. This segmentation allows the long data path to be broken into smaller segments, each with its own skew correction capability, thereby maintaining signal integrity across the entire extended channel while supporting high resolution displays.
2Speed
If the driving frequency is increased to achieve higher resolution, then the data transmission speed is improved, but skew between clock and data causes data sampling errors
Solution Approach 1:
Bi-directional deskew buffer parts are introduced as intermediary components between adjacent channel blocks. These buffers receive clock signals from one channel block and data signals from another, perform skew correction by buffering and re-synchronizing the signals, and output corrected signals. This intermediary mechanism enables high-speed data transmission while maintaining accurate sampling by compensating for timing differences caused by varying path lengths.
3Quantity of substance
If the chip length is increased to accommodate more channels, then the channel count is improved, but the skew problem between clock and data worsens
Solution Approach 1:
The chip is segmented into multiple channel blocks with bi-directional deskew buffer parts positioned between them. Each buffer part independently corrects skew for its adjacent channels, distributing the skew correction function across the entire chip. This allows the chip length to be extended to accommodate more channels while maintaining reliable skew correction through the distributed buffer architecture.
Data Source
AI summary
The present disclosure relates to a data driver circuit capable of overcoming a limitation in frequency by correcting a skew between a clock and data even when a frequency and the number of channels are increased, and the data driver circuit according to an aspect may include a shift register configured output sampling signals in response to a clock, a first latch part configured to sample and latch data of each channel in response to each of the sampling signals, and a bi-directional deskew buffer part disposed between a stage of a first channel and a stage of a second channel belonging to the shift register and between a first latch of a first channel and a second latch of a second channel belonging to the first latch part and configured to buffer a clock input from the stage of the first channel.