Data Driver Delay Clock Synchronization for Display Uniformity
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Solution Overview
Problem
As display panel sizes increase and operating speeds rise, signal delays in gate drivers lead to uneven image quality and a 'dim phenomenon' at boundaries between display areas driven by different data driver chips, due to signal delay deviations.
Innovation Solution
A data driver design incorporating a first latch, a second latch, a digital-to-analog converter, and an output buffer, which generates and transmits delay clock signals to adjacent chips to synchronize data voltage output, preventing data mix-ups and ensuring consistent image display across chip boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the display panel size increases and operating speed rises, then the display resolution and refresh rate are improved, but signal delay in the gate driver path increases causing uneven charging rates and poor image quality
Solution Approach 1:
The patent introduces delay clock signals with adjustable delay times for different data driver chips. By changing the timing parameter of the clock signals based on the specific chip's delay characteristics, the system compensates for signal delay variations and achieves synchronized data voltage output across all display areas, resolving the contradiction between high refresh rate operation and signal delay.
2Device complexity
If the data driver is separated into plural chips, then the device can be mounted after separation to reduce complexity, but signal delay deviation between chips causes dim phenomenon at boundaries between display areas
Solution Approach 1:
The patent implements a feedback mechanism where delay information from one data driver chip is transmitted to adjacent chips. Each chip adjusts its delay clock signal based on the delay characteristics of neighboring chips, creating a feedback loop that equalizes signal delay across all chips and eliminates the dim phenomenon at display area boundaries.
Solution Approach 2:
The patent dynamically adjusts the delay time parameter of clock signals for each data driver chip based on its specific delay characteristics and the delay information received from adjacent chips. This parameter adjustment ensures that all chips output data voltages simultaneously, compensating for manufacturing variations and achieving consistent display quality across segmented chips.
3Reliability
If two latches are used to store line data, then data mixing between lines is prevented, but the device complexity increases
Solution Approach 1:
The patent divides the data storage function into separate latch circuits for different data lines. By segmenting the data handling process and using dedicated latches for each line, the system prevents data mixing while maintaining clear functional separation. This segmentation approach, combined with the delay clock mechanism, ensures reliable data output without excessive complexity.
Data Source
AI summary
A data driver includes a first latch, a second latch, a digital-to-analog converter, and an output buffer. The first latch sequentially stores first line data in response to a first sampling signal and outputs the stored data in parallel. The second latch sequentially stores second line data in response to a second sampling signal and outputs the stored data in parallel. The digital-to-analog converter converts the parallel data provided from one of the first and second latches to data voltages. The output buffer outputs the data voltages in response to a delay clock.