Data Driver Resistance Calibration for Stable Slice Ratio
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Solution Overview
Problem
High-speed SerDes designs face challenges with resistance-matching resolution loss due to digital calibration loops that fail to maintain a consistent 2:1 ratio of MSB to LSB driver slices across process, voltage, and temperature (PVT) corners, leading to bandwidth limitations and increased output capacitance.
Innovation Solution
Analog resistance calibration technique that fixes the number of driver slices and uses bias circuits with replica transistors and operational amplifiers to maintain consistent resistance across PVT corners, ensuring a desired output resistance match with the transmission line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital calibration loop is used to adjust slice number for resistance matching, then resistance matching is achieved, but output capacitance increases and bandwidth is limited
Solution Approach 1:
The patent changes the calibration approach from digital (discrete slice counting) to analog (continuous resistance adjustment via bias circuits). The bias circuits adjust transistor operating points to achieve precise resistance matching without increasing slice number, thereby avoiding increased output capacitance and maintaining bandwidth.
2Adaptability or versatility
If digital calibration loop adjusts slice number across PVT corners, then resistance matching is maintained, but slice ratio consistency (2:1 MSB:LSB) is lost
Solution Approach 1:
The patent replaces the digital calibration mechanism (slice selection via digital control) with an analog bias control mechanism. The bias circuits continuously adjust transistor characteristics to maintain both resistance matching and slice ratio consistency across PVT corners, eliminating the quantization errors inherent in digital slice counting.
3Adaptability or versatility
If number of driver slices is increased to cover PVT corner variations, then resistance matching range is extended, but output capacitance and pre-driver power consumption increase
Solution Approach 1:
The patent changes from adjusting the number of active slices to adjusting the bias parameters of existing slices. The bias circuits modify transistor operating points to achieve resistance matching across PVT corners, allowing the same physical slices to adapt to different conditions without increasing output capacitance or pre-driver power consumption.
4Measurement precision
If digital calibration loop is used, then resistance matching is achieved, but resolution loss occurs due to inability to maintain exact slice division ratio
Solution Approach 1:
The patent replaces digital slice selection with analog bias control, enabling continuous adjustment of resistance values. This eliminates the discrete steps inherent in digital calibration, allowing exact maintenance of slice division ratios (2:1 MSB:LSB) and preventing resolution loss while achieving precise resistance matching.
Data Source
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AI summary
A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.