Data Driving Circuit with Output Delay Controller for Display Devices
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Solution Overview
Problem
Display devices with a single side driving structure face issues with non-uniform resistive-capacitive (RC) load due to varying scan line lengths, leading to synchronization deviations and display quality degradation.
Innovation Solution
A display device with a timing controller that adjusts data signal output times based on position information, using an output delay controller with a clock frequency divider, reference period generator, and delay time determiner to control delay times of data signals transmitted to scan lines, ensuring synchronized data charging across the display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single side driving structure is used to reduce bezel width, then the device size is reduced, but non-uniform RC load occurs causing synchronization deviation and display quality degradation
Solution Approach 1:
The patent applies local quality by setting different delay times for different data lines based on their specific positions and RC load characteristics. The output delay controller adjusts delay times individually for each data line group, making the delay characteristic match the local RC load characteristic at each position, thereby resolving the synchronization deviation caused by non-uniform RC load in the single side driving structure
Solution Approach 2:
The patent changes the delay time parameter dynamically based on position information of pixel rows and RC load characteristics. The output delay controller receives position information and adjusts the delay time parameter for each data line group accordingly, transforming the fixed delay structure into a variable delay structure that adapts to different positions and RC load conditions
2Device complexity
If scan lines are formed with different lengths to accommodate single side driving, then device complexity is reduced, but timing synchronization between scan signals and data signals deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating and setting appropriate delay times for each data line group based on their RC load characteristics and position information before data signal output. The output delay controller pre-adjusts the delay time parameter according to position information of pixel rows, ensuring that data signals are output at the correct timing to synchronize with scan signals before they reach the pixels
Data Source
AI summary
A display device including: a display area including pixels connected to data lines and scan lines, the display area including a plurality of signal output lines connected to each of the scan lines through a contact; a data driver including a first data driving circuit at a side of the display area; a scan driver disposed at the side of the display area; and a timing controller, wherein the first data driving circuit includes: output buffers which respectively output data signals to first to k-th data lines (k is an integer greater than 2) of the data lines; and an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are supplied.