Data Driving Circuit Equalizer Setting via Intra-Panel Interface
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Display devices face signal distortion issues due to varying data rates and transmission line characteristics across different display devices, requiring a distinct interface for setting equalizer values for each data driving circuit, which is not efficiently addressed by existing technologies.
Innovation Solution
A data driving circuit capable of setting an equalizer using an intra-panel interface, where the equalizer setting value is transmitted at a low rate initially and then the clock training signal and image data are sent at a higher rate, allowing simultaneous equalizer setting across multiple data driving circuits without the need for a separate interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a separate interface is used for setting equalizer values, then equalizer setting precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the equalizer setting function with the existing intra-panel interface by embedding setting values within data control signals. This eliminates the need for a separate interface while maintaining precise equalizer configuration across different display devices with varying data rates and transmission line characteristics.
Solution Approach 2:
The intra-panel interface is designed to serve multiple functions: transmitting data control signals for normal operation and embedding equalizer setting values within the same signal stream. This multi-functionality reduces device complexity while preserving the precision needed for equalizer configuration.
2Productivity
If data rate of intra-panel interface is increased, then productivity is improved, but signal integrity deteriorates
Solution Approach 1:
The equalizer setting values are transmitted and configured before high-speed data transmission begins. The timing controller sends control signals containing setting values at a manageable rate, allowing the data driving circuit to pre-configure its equalizer. This preliminary action ensures signal integrity is optimized before the high data rate transmission starts, preventing distortion issues.
Solution Approach 2:
The system dynamically adjusts the transmission rate based on the type of signal being sent. During the equalizer setting phase, data is transmitted at a lower rate to ensure accurate reception of setting values. During normal operation, the data rate increases to high speeds for productivity, while the equalizer continuously compensates for distortion.
3Reliability
If equalizer setting value is transmitted at low rate, then signal integrity is improved, but productivity decreases
Solution Approach 1:
The transmission process is divided into periodic phases: a setup phase where equalizer setting values are transmitted at a lower rate to ensure signal integrity, followed by a data transmission phase where high-speed data is sent at full productivity. This periodic alternation between low-rate configuration and high-rate data transmission resolves the contradiction by ensuring both signal integrity and productivity are optimized at different times.
Data Source
AI summary
A display device includes a display panel having pixels. A timing controller generates a first control signal and data control signals. Data driving circuits each recover a data signal from a corresponding data control signal of the data control signals in response to the first control signal, generate a data voltage corresponding to the data signal, and provide the data voltage to the display panel. Each of the data driving circuits includes: a setting unit configured to acquire a setting value from the data control signal; an equalizer configured to compensate for distortion of the corresponding data control signal according to the setting value to output compensated data control signal; and a recoverer configured to recover a clock signal from the compensated data control signal and recover the data signal from the compensated data control signal based on the clock signal.