Data Driving Circuit Signal Timing Adjustment for Display Noise Reduction
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Solution Overview
Problem
Existing data driving circuits in display devices face challenges in optimizing output timing, leading to potential noise and degradation in image signals due to Electro Magnetic Interference (EMI) and delayed falling edges of output enable signals, which affect display quality.
Innovation Solution
A data driving circuit design that includes a signal generator to adjust the start timing of the active duration of the latch enable signal to begin after the inactive duration of the output enable signal starts, ensuring the active duration of the latch enable signal is not overlapped with the active duration of the output enable signal, and operating in multiple modes to maintain stable image signal output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the latch enable signal and output enable signal are generated with overlapping active durations, then the circuit operation is simplified, but noise and EMI occur in the image signal
Solution Approach 1:
The patent segments the enable signal durations by introducing a signal generator that divides the active duration of the latch enable signal into multiple periods, ensuring they do not overlap with the active duration of the output enable signal. This segmentation prevents simultaneous activation that causes EMI while maintaining circuit functionality through structured temporal separation.
Solution Approach 2:
The signal generator performs preliminary action by pre-configuring the timing relationships between enable signals before the image signal processing occurs. By establishing that the active duration of the latch enable signal starts after the inactive duration of the output enable signal begins, the system proactively prevents EMI conditions from arising during signal overlap.
2Duration of action of moving object
If the active duration of the latch enable signal overlaps with the active duration of the output enable signal, then signal processing is continuous, but the falling edge delay degrades image signal quality
Solution Approach 1:
The patent segments the timing of enable signals to create distinct operational phases. By dividing the signal processing into separate non-overlapping active durations for latch and output enable signals, the system maintains continuous processing through proper sequencing while preventing the quality degradation caused by delayed falling edges during overlap conditions.
Solution Approach 2:
The signal generator dynamically adjusts the timing of enable signals based on operational mode. In the first operating mode, the output enable signal is maintained in an active level to keep the switch turned on, while in the second operating mode, dynamic timing adjustment ensures the active duration of the latch enable signal starts after the inactive duration of the output enable signal, adapting to different display requirements.
3Object-affected harmful factors
If the latch enable signal timing is adjusted to prevent overlap with output enable signal, then EMI is reduced, but the circuit timing control becomes more complex
Solution Approach 1:
The signal generator serves multiple functions: it generates both the latch enable signal and the output enable signal, manages timing relationships between them, and adapts to different operating modes. This multi-functionality consolidates the complexity into a single component rather than requiring separate control circuits for each signal, making the timing control more manageable despite the increased functional requirements.
Data Source
AI summary
A data driving circuit of a display device is disclosed that includes a latch circuit to latch a data signal in response to a latch enable signal and to output a first signal, a level shifter to output a second signal obtained by changing a voltage level of the first signal, a digital-analog converter to output a third signal obtained by converting the second signal into an analog signal, an amplifier to output a fourth signal obtained by amplifying the third signal, a switch to output the fourth signal in a form of an image signal, in response to an output enable signal, and a signal generator to generate the latch enable signal and the output enable signal. The signal generator adjusts a start timing of the active duration of the latch enable signal, such that the active duration of the latch enable signal starts, after the inactive duration of the output enable signal starts.