Data Equalizing Circuit Using Dispersion-Based Transition Detection
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Solution Overview
Problem
Conventional data equalizing circuits face challenges in precisely detecting data transitions with high frequency sampling clocks, leading to increased hardware burden and power consumption.
Innovation Solution
A data equalizing circuit that divides data into N periods, uses multi-phase locked loops to generate clocks with a frequency lower than the data frequency, and calculates dispersion values of data transition frequencies for 1/N periods to determine the optimal control code, reducing hardware burden and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high frequency sampling clocks are used to precisely detect data transitions, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent divides n cycles of data into N periods and performs detection on segmented portions rather than requiring continuous high-frequency sampling across the entire data stream. This segmentation allows lower frequency clocks to achieve equivalent detection precision by concentrating sampling efforts on critical transition regions.
Solution Approach 2:
The patent changes the parameter of clock frequency from high to low (1/n times the data frequency) while compensating through multi-phase clock generation and strategic sampling. By adjusting the phase relationships and sampling timing rather than relying on high frequency, the system maintains detection precision while reducing hardware burden.
2Measurement precision
If high frequency sampling clocks are used to precisely detect data transitions, then measurement precision is improved, but power consumption increases
Solution Approach 1:
By segmenting the detection process into N periods across n cycles and using lower frequency clocks, the patent reduces the total number of sampling operations required. This segmentation allows the system to achieve precise transition detection with fewer clock cycles, directly reducing power consumption associated with high-frequency clock generation and processing.
Solution Approach 2:
The patent employs periodic multi-phase clock signals with phase differences to sample data transitions. This periodic action with controlled phase relationships enables precise detection at lower frequencies by strategically sampling at critical phases, reducing continuous high-power consumption of high-frequency clocks while maintaining detection accuracy.
3Measurement precision
If more sampling clocks with high frequency are generated to determine data transition distribution, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent generates N number of clocks with phase differences that serve multiple functions: they segment the data cycles, provide sampling references, and enable transition detection across different phases. This multi-functional clock system replaces what would otherwise require multiple separate high-frequency sampling circuits, reducing overall device complexity while maintaining precision.
Data Source
AI summary
A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.