Data Error Detection Module for Automotive Memory Safety
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Solution Overview
Problem
Current data processing devices in automotive systems, using SECDED error correction, fail to meet the high ASIL-D functional safety requirements due to insufficient failure detection mechanisms in memory controllers, leading to erroneous correction of 3-bit errors and inadequate fault detection rates, limiting the system to ASIL-B safety levels even when combined with high-ASIL processors.
Innovation Solution
Incorporating a data error detection module that stores CRCs of data in DRAM, providing end-to-end protection and enabling fault detection rates that satisfy ASIL-D levels, with mechanisms for detecting faults and using redundant modules to enhance fault detection coverage, and employing appropriate error detection codes for the data bus to meet high ASIL requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SECDED error correction is used in the memory controller, then 1-bit error correction and 2-bit error detection are achieved, but 3-bit errors may be erroneously corrected to wrong data, limiting the failure detection rate to ASIL-B level
Solution Approach 1:
The patent introduces a data error detection module as an intermediary between the memory controller and the processor. This module performs additional error detection using CRC (Cyclic Redundancy Check) codes, which act as a mediator to detect errors that SECDED cannot reliably detect, including 3-bit errors. The error detection module receives data from the memory controller, verifies integrity using CRC, and only passes valid data to the processor, thereby preventing erroneous corrections from affecting system reliability.
Solution Approach 2:
The patent implements a redundant data error detection module that copies the error detection function. By having another instance of the error detection module that independently verifies data integrity using CRC codes, the system can detect errors that the primary memory controller's SECDED mechanism might miss. This copying approach provides parallel verification without requiring the memory controller itself to be redesigned at ASIL-D level.
2Reliability
If the memory controller is designed at ASIL-B level, then the circuit scale is suppressed, but the functional safety cannot meet ASIL-D requirements when combined with high-ASIL processors
Solution Approach 1:
The patent segments the error detection function into separate components: the memory controller maintains its simpler ASIL-B design with SECDED, while a separate data error detection module handles the additional ASIL-D required error detection using CRC codes. This segmentation allows the memory controller to remain relatively simple while the system as a whole achieves ASIL-D functional safety through the addition of the dedicated error detection module that operates independently.
Solution Approach 2:
The data error detection module serves as an intermediary that bridges the gap between ASIL-B memory controller capabilities and ASIL-D system requirements. It receives data from the ASIL-B compliant memory controller, performs enhanced error detection using CRC, and ensures that only error-free data reaches the processor. This intermediary approach allows the system to meet ASIL-D functional safety without requiring the memory controller itself to be redesigned at the higher safety level.
3Reliability
If CRC of data is stored in DRAM to provide end-to-end protection, then ASIL-C and ASIL-D safety levels are achieved, but the device complexity increases
Solution Approach 1:
The data error detection module is designed with multi-functionality to reduce overall system complexity. It performs multiple functions including: receiving data from the memory controller, calculating CRC codes for error detection, storing CRC values in a buffer, comparing CRC values to detect errors, and controlling data transmission to the processor. By consolidating these functions into a single modular unit, the patent achieves end-to-end ASIL-D protection without proportionally increasing device complexity.
Data Source
AI summary
In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.