Data Error Measuring Circuit for Semiconductor Memory
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Solution Overview
Problem
Conventional semiconductor memory apparatuses with ECC can only detect multi-bit errors and fail to detect one-bit errors, leading to reduced reliability as they cannot identify defective cells storing 8-bit data.
Innovation Solution
A data error measuring circuit that includes a data error correction unit, a data selection unit, and a test result output unit, which compares input data with parity data to correct errors and outputs a test result signal, enabling discrimination between one-bit and multi-bit errors by selecting and comparing data signals based on a test selection signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC is used to correct one-bit errors, then data reliability is improved, but the ability to detect multi-bit errors and defective cells is lost
Solution Approach 1:
The patent divides the error detection and measurement function into separate modules: a data error correction unit for correcting one-bit errors, a data selection unit for selecting data based on test selection signals, and a test result output unit for detecting errors. This segmentation allows the system to simultaneously perform correction and detection functions that were combined in conventional ECC.
Solution Approach 2:
The patent introduces a test selection signal as an intermediary mechanism that controls the data selection unit. This intermediary signal enables the system to switch between different operational modes (correction mode and detection mode) without requiring separate hardware for each function, thus resolving the contradiction between correction capability and detection capability.
2Ease of operation
If general data error measuring circuit is used to correct errors, then one-bit errors are corrected, but multi-bit errors and defective cells cannot be detected
Solution Approach 1:
The patent makes the error measurement circuit dynamic by introducing a test selection signal that can switch the circuit between different operational states. When the test selection signal indicates correction mode, the circuit corrects one-bit errors. When the test selection signal indicates detection mode, the circuit detects multi-bit errors and defective cells. This dynamic switching resolves the contradiction between ease of operation and measurement precision.
Solution Approach 2:
The patent designs the data error measuring circuit to perform multiple functions: correcting one-bit errors, detecting multi-bit errors, and identifying defective cells. By making the circuit universal and capable of performing these different functions through the test selection signal, the patent eliminates the need for separate circuits for each function, thereby improving both ease of operation and measurement precision.
3Reliability
If semiconductor memory apparatus stores data with ECC, then data integrity is maintained, but defective cells storing 8-bit data cannot be identified
Solution Approach 1:
The patent implements a feedback mechanism where the test result output unit compares the selected data with the parity data and outputs a test result signal. This feedback signal indicates whether errors were detected during the measurement process, thereby identifying defective cells. The feedback mechanism allows the system to maintain data integrity through ECC while simultaneously being able to detect and report defective cells.
Data Source
AI summary
A data error measuring circuit for a semiconductor memory apparatus includes a data error correction unit that compares data with parity data to correct data, a data selection unit that outputs the data or the corrected data as selected data in response to a test selection signal, and a test result output unit that receives the selected data and the parity data to output a test result signal in response to the test selection signal.