Data Flow Control Mechanism for Video Processing Pipeline Bottlenecks

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Solution Overview

Problem

Conventional video processing systems, such as PVRs and DVRs, experience data pipeline congestion due to long packet processing times, leading to inefficiencies in data flow and potential bottlenecks that affect overall bit rate.

Innovation Solution

A data flow control system utilizing a programmable processor and switching circuitries to monitor and regulate data processing along the pipeline, postponing processing at bottleneck stations until conditions improve, ensuring smooth data transmission and maintaining bit rate by executing software/firmware to manage data flow and buffer levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If packets are processed thoroughly for index table generation, then data processing completeness is improved, but data pipeline throughput deteriorates due to long processing times

Engineering Contradiction:
Improvedata processing completenessVSAvoiddata pipeline throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The data processing pipeline is divided into multiple processing stations, each responsible for specific tasks. This segmentation allows parallel processing of different packet operations, reducing the time each station spends on individual packets while maintaining overall processing completeness through coordinated operation across stations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The flow control mechanism dynamically adjusts packet transmission based on real-time buffer status at each processing station. When a station is busy, upstream stations are blocked; when buffers are available, transmission resumes. This dynamic adaptation optimizes throughput while ensuring complete processing by coordinating station operations based on actual workload conditions.

Inventive Principle:
Principle #15Dynamics

2Manufacturing precision

If processing time at bottleneck stations is extended for thorough packet processing, then data processing quality is improved, but downstream data flow stability deteriorates

Engineering Contradiction:
Improvedata processing qualityVSAvoiddownstream data flow stability
Core Design Contradiction:
Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

Each processing station monitors its own buffer status and provides feedback to upstream stations about packet availability and processing state. This feedback mechanism allows the system to adapt packet transmission to actual processing capacity, ensuring that processing quality is maintained while preventing downstream flow instability through coordinated response to buffer conditions.

Inventive Principle:
Principle #23Feedback

3Reliability

If flow control is implemented to prevent congestion, then data pipeline reliability is improved, but system complexity increases due to additional control mechanisms

Engineering Contradiction:
Improvedata pipeline reliabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The flow control mechanism operates autonomously at each processing station, using local buffer status information to automatically block or allow packet transmission without requiring external intervention. This self-service approach improves reliability by preventing congestion through distributed decision-making, while minimizing system complexity by eliminating the need for centralized control or complex coordination protocols.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8526303B2Flow control mechanism in a data processing pipeline
Publication Date: 2013.09.03 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8526303B2 patent drawing
  • US8526303B2 patent drawing
  • US8526303B2 patent drawing

AI summary

Herein described are at least a system and a method for regulating data flow in a data pipeline that may be used in a video processing system. The system comprises a processor, one or more data buffers, and one or more processing stations. The one or more data buffers may be used to buffer corresponding processing stations. Each of the one or more processing stations may comprise a switching circuitry that is used to inhibit data transmission when a hold signal is received from the processor. The processor may send the signal in response to a feedback control signal generated by the one or more processing stations. The method may comprise determining if the processing time of a processing station exceeds a specified time. The method further comprises generating a feedback control signal to a processor if the specified time is exceeded.