Two-Pass Data Flow Graph Mapping for Processor Arrays
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Solution Overview
Problem
Existing methods for implementing applications on processor arrays do not effectively minimize data movement and memory conflicts, which are crucial for efficient execution, as they primarily focus on timing and do not consider architectural constraints or data flow optimizations.
Innovation Solution
A method involving a two-pass technique to map a data flow graph onto an array of data processing engines, using Integer Linear Programming to minimize DMA engine usage and memory conflicts, and inserting additional buffers as needed to optimize data flow and resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If existing mapping methods are used that focus primarily on timing, then timing constraints may be met, but data movement and memory conflicts are not minimized
Solution Approach 1:
The mapping process is divided into two distinct passes: a first pass that performs initial mapping with timing constraints, and a second pass that optimizes data movement and memory conflicts. This segmentation allows each pass to focus on specific optimization goals without compromising the other, thereby reducing data movement while maintaining timing requirements.
Solution Approach 2:
The first pass performs preliminary mapping that establishes timing feasibility before the second pass optimizes data movement. By preparing the mapping structure in advance with timing constraints satisfied, the second pass can focus solely on minimizing data movement and memory conflicts without needing to re-evaluate timing constraints.
2Productivity
If existing mapping methods are used that focus primarily on timing, then timing constraints may be met, but memory conflicts are not minimized
Solution Approach 1:
The mapping process is divided into two distinct passes: a first pass that performs initial mapping with timing constraints, and a second pass that optimizes data movement and memory conflicts. This segmentation allows each pass to focus on specific optimization goals without compromising the other, thereby reducing data movement while maintaining timing requirements.
Solution Approach 2:
The second pass uses information from the first pass mapping results to identify and resolve memory conflicts. By analyzing the initial mapping configuration and providing feedback for optimization, the system can adjust the mapping to minimize memory conflicts while preserving the timing feasibility established in the first pass.
3Device complexity
If the number of DMA engines is limited, then device complexity is reduced, but data movement efficiency deteriorates
Solution Approach 1:
Instead of providing enough DMA engines for every possible data movement operation, the system uses a limited number of DMA engines and compensates by optimizing the mapping to minimize the total amount of data movement. The second pass specifically targets reduction of data movement requirements, allowing fewer DMA engines to handle the reduced data transfer workload efficiently.
Solution Approach 2:
The mapping optimization acts as an intermediary that reduces the burden on DMA engines by minimizing data movement requirements before data transfer occurs. By optimizing the mapping configuration to reduce the volume and frequency of data transfers, the limited DMA engines can handle data movement more efficiently without requiring additional hardware resources.
Data Source
AI summary
Implementing an application using a plurality of data processing engines (DPEs) can include, in a first pass, mapping, using computer hardware, a data flow graph onto an array of DPEs by minimizing direct memory access (DMA) circuit usage and memory conflicts in the array of DPEs and, in response to determining that a mapping solution generated by the first pass requires an additional DMA circuit not specified by the data flow graph, inserting, using the computer hardware, additional buffers into the data flow graph. In a second pass, the additional buffers can be mapped, using the computer hardware, onto the array of DPEs by minimizing the memory conflicts in the array of DPEs.