Data Flow Graph Processor for High-Dimensional AI Execution
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Solution Overview
Problem
Traditional computing systems, such as CPUs and GPUs, face inefficiencies in processing complex AI tasks due to the need for intricate step-by-step execution of assembly instructions, leading to high energy consumption and resource wastage.
Innovation Solution
Data Flow-Based Computing systems utilize high-level graph representations to map hardware control flows, enabling efficient execution of operations through multi-threading and simplifying the processing of complex computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional CPUs and GPUs execute assembly instructions step-by-step, then computational tasks can be completed, but energy consumption increases and processing efficiency decreases
Solution Approach 1:
The patent replaces the traditional mechanical instruction-execution model (fetch-decode-execute cycle) with a data-flow driven model where operations are triggered automatically when data becomes available. This substitution eliminates the need for sequential instruction processing and reduces energy consumption by performing only necessary computations.
Solution Approach 2:
The system performs preliminary actions by pre-computing and caching intermediate results in a results cache before they are actually needed. This allows the data-flow processor to retrieve pre-computed values instead of re-computing them, significantly improving efficiency and reducing energy usage for repetitive computational patterns.
2Productivity
If traditional processors use intricate instruction execution with dependencies and data hazards, then computational accuracy is maintained, but processing time increases
Solution Approach 1:
The patent replaces the traditional instruction-execution mechanism with a data-flow driven execution model. Instead of following sequential instructions with dependency checking, the system automatically triggers operations when input data is available and results are consumed, eliminating data hazard checks and reducing execution time.
Solution Approach 2:
The computational graph is segmented into independent operation nodes that can execute concurrently. Each node processes data independently when inputs are ready, allowing parallel execution of multiple operations without traditional instruction dependencies, thus reducing overall execution time.
3Device complexity
If traditional computing systems use high-level graph representations, then operational mapping becomes simplified, but hardware complexity increases
Solution Approach 1:
The patent uses a results cache that stores intermediate computational results, effectively creating copies of data that can be reused multiple times. This copying mechanism simplifies the mapping of high-level graph operations to hardware execution by allowing the same computed value to be referenced by multiple downstream operations without re-computation.
Solution Approach 2:
The results cache acts as an intermediary between computation operations and data consumers. It mediates the data flow by storing results temporarily and supplying them to multiple operations as needed, simplifying the control flow logic and making the mapping from high-level graphs to hardware execution more straightforward.
Data Source
AI summary
A Data Flow processor (DFP or DFPU) including a plurality of loop registers to effectively control the processing of multi-dimensional data; and a plurality of stride registers that are operable for precise addressing of data, enabling comprehensive management of data fetching, execution, accumulation, and result write-back processes; and wherein the processor is configured to be operable for high-dimensional computing.