Multi-Core Data Flow Tagging for Silent Corruption Detection

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Solution Overview

Problem

Conventional methods for protecting data within device platforms, such as dual and triple modular redundancy, require excessive resources and increase processing time and costs, while failing to detect silent data corruption errors effectively during tasks like encryption and decryption.

Innovation Solution

A multi-core computing system that utilizes a single pass flow to detect silent data corruption errors by tagging processed data with a core identifier, allowing a different processing entity to perform reverse operations and mitigate double errors caused by faulty processors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dual and triple modular redundancy methods are used to protect data, then data reliability is improved, but resource consumption increases excessively and processing time increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidresource consumption
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system segments the redundancy check into targeted portions rather than requiring full modular redundancy of all data. By identifying and checking only critical segments or portions of data that are most susceptible to silent corruption, the system achieves improved reliability without proportionally increasing resource consumption across the entire data set.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies enhanced protection measures locally to specific data portions that are most vulnerable to silent corruption, rather than uniformly applying redundancy across all data. This localized approach focuses computational resources on high-risk areas, improving overall data reliability while minimizing unnecessary resource consumption in low-risk areas.

Inventive Principle:
Principle #3Local quality

2Reliability

If dual and triple modular redundancy methods are used to protect data, then data reliability is improved, but processing time increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The redundancy verification process is segmented into targeted checks rather than requiring complete re-processing of all data through multiple redundant paths. By segmenting the verification into specific critical checks, the system maintains high data reliability while significantly reducing the time penalty associated with full modular redundancy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary integrity checks and identifies vulnerable data portions before main processing occurs. This preliminary action allows the system to apply redundancy measures only where and when needed, rather than universally applying time-consuming redundant processing to all data, thus maintaining reliability while reducing overall processing time.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If conventional redundancy methods are used, then data protection is provided, but silent data corruption errors are not detected effectively

Engineering Contradiction:
Improvedata protectionVSAvoiderror detection capability
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent implements specialized detection mechanisms focused on specific data portions and corruption patterns that are most likely to exhibit silent errors. By applying targeted detection methods to vulnerable areas rather than generic redundancy checks across all data, the system achieves superior silent error detection capability while maintaining data protection.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system introduces intermediary verification steps between data processing stages, where specific checks are performed to detect silent corruption that conventional redundancy methods miss. These intermediary checks act as mediators that bridge the gap between standard redundancy and comprehensive error detection, enhancing detection precision without requiring full triple modular redundancy.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Reliability

If dual and triple modular redundancy are used, then data protection is improved, but device complexity and costs increase

Engineering Contradiction:
Improvedata protectionVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system segments the protection mechanism into manageable portions, implementing redundancy and detection only where necessary rather than uniformly across the entire system. This segmentation reduces device complexity by eliminating unnecessary redundant components and processes while maintaining data protection in critical areas.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies enhanced protection and detection mechanisms locally to specific data portions and processing stages where silent corruption is most likely to occur, rather than uniformly applying complex redundancy systems throughout. This localized approach reduces overall device complexity while maintaining robust data protection where it matters most.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12072760B2Methods and apparatus to control execution of tasks in a computing system
Publication Date: 2024.08.27 INTEL CORP
  • US12072760B2 patent drawing
  • US12072760B2 patent drawing
  • US12072760B2 patent drawing

AI summary

Methods, apparatus, systems and articles of manufacture are disclosed to control execution of tasks in a computing system. The methods, apparatus, systems and articles of manufacture include at least one storage device and at least one processor to, execute instructions to at least obtain a request to perform an inverse operation on a data flow, the data flow previously transformed during a forward operation, determine a first processor core that executed the forward operation, the data flow including an identifier of the first processor core, and transmit the data flow to a second processor core to perform the inverse operation.