Data Frame Buffer Management for Image Processing Delays

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Solution Overview

Problem

In data processing, particularly in image processing, the increasing performance of image processing modules leads to data interaction delays between video input sources and processing modules, resulting in frame skips during full-frame processing, which affects processing accuracy.

Innovation Solution

A data processing system with multiple data frame buffer regions and a state register is implemented, allowing cyclic use of buffer regions to manage data frame processing independently of the image processing controller's state updates, thereby reducing delays and preventing frame skips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If image processing module performance is improved, then processing speed increases, but data interaction delay between video input source and processing module increases

Engineering Contradiction:
Improveimage processing module performanceVSAvoiddata interaction delay
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The buffer memory is divided into multiple buffer regions (first buffer region, second buffer region, etc.), allowing parallel data storage and processing. This segmentation enables the system to maintain high processing performance while reducing interaction delays through concurrent operations in different buffer regions.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If full-frame processing is performed, then processing completeness is improved, but frame skips occur affecting processing accuracy

Engineering Contradiction:
Improveprocessing accuracyVSAvoidframe processing continuity
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The system performs preliminary actions by pre-configuring multiple buffer regions and establishing buffer region management logic before processing begins. The state register is pre-initialized to track buffer region states, enabling the system to maintain processing accuracy while preventing frame skips through proactive buffer management.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The state register provides continuous feedback on the states of multiple buffer regions, enabling the buffer region management logic to dynamically adjust processing operations. This feedback mechanism ensures processing accuracy is maintained while preventing frame skips by coordinating read/write operations based on real-time buffer states.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11677902B2Data processing method and related product
Publication Date: 2023.06.13 SHENZHEN CORERAIN TECH CO LTD
  • US11677902B2 patent drawing
  • US11677902B2 patent drawing
  • US11677902B2 patent drawing

AI summary

Provided is a data processing system. The system includes a data source, a data receiver, a plurality of source code data frame buffer regions, a data processing module and a state register. The data source is configured to generate a data frame, the data receiver is configured to receive the data frame, and write the data frame into one of a plurality of data frame buffer regions, each of the plurality of source code data frame buffer regions is configured to store a data frame to be processed, the data processing module is configured to perform subsequent processing on data and the state register is configured to store a state of the system and states of the plurality of source code data frame buffer regions.