Data Handover Unit for Clock Domain Crossing
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Solution Overview
Problem
High-speed data transfer between clock domains with different frequencies poses challenges due to increased power consumption and latency in existing solutions, such as high-speed FIFOs, and critical timing issues with barrel shifters.
Innovation Solution
A data handover unit with a selector stage, storage unit, and output unit that samples incoming data with a first clock signal, stores it in a ring register, and reads out data bits in parallel with a second clock signal, reducing power consumption and avoiding critical timing conditions by limiting the number of storage elements and using a position counter for efficient data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-speed FIFO is used to transfer data between clock domains with different frequencies, then data transfer reliability is improved, but power consumption increases and latency increases
Solution Approach 1:
The patent divides the data transfer process into two distinct phases: a capture phase where data is sampled and stored in storage elements during the high-speed clock domain, and a transfer phase where the captured data is output during the lower-speed clock domain. This segmentation allows the system to operate at high speed during capture without requiring high-speed operation throughout the entire transfer process, thereby reducing power consumption while maintaining reliability.
Solution Approach 2:
The patent implements preliminary action by capturing and storing data in the storage elements during the high-speed clock domain before transferring to the lower-speed clock domain. The storage elements are pre-loaded with data bits that will be output later at the lower speed, eliminating the need for continuous high-speed operation and reducing overall power consumption while ensuring data transfer reliability.
2Reliability
If a high-speed FIFO is used to transfer data between clock domains with different frequencies, then data transfer reliability is improved, but latency increases
Solution Approach 1:
The patent segments the data transfer into discrete capture and transfer phases, allowing data to be captured quickly during the high-speed clock domain and then output at the lower speed without requiring the FIFO to buffer data for extended periods. This segmentation reduces the waiting time and improves throughput compared to traditional FIFO approaches.
Solution Approach 2:
By preliminarily capturing and storing data in the storage elements during the high-speed clock domain, the system prepares data for immediate output when the lower-speed clock domain is ready, minimizing delays and reducing latency compared to traditional FIFO methods that require continuous synchronization.
3Productivity
If a barrel shifter is used to transfer data from pointer to storage, then data transfer capability is improved, but timing complexity increases
Solution Approach 1:
The patent extracts the timing complexity issue by removing the barrel shifter from the critical path. Instead of using a barrel shifter that requires precise timing control to shift data between pointer and storage, the invention directly stores sampled data bits into storage elements during the capture phase, eliminating the timing-sensitive shifting operation and simplifying the overall timing requirements.
Solution Approach 2:
The patent performs preliminary storage of data bits into the storage elements during the capture phase before any output occurs. This preliminary action eliminates the need for subsequent timing-critical shifting operations, as data is already positioned in the storage elements ready for output at the lower speed, thereby reducing timing complexity.
Data Source
AI summary
The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by the output unit.