Data Holding Circuit Layout for Compact Flip-Flop Feedback
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Solution Overview
Problem
Conventional data holding circuits face challenges in miniaturization due to the need for larger p-channel MOS transistors in feedback paths, leading to increased chip size, and struggle with reduced drive capability when inverting states held in flip-flops.
Innovation Solution
A data holding circuit design that uses a combination of p-channel and n-channel MOS transistors in specific configurations to transmit data signals and inverted data signals, avoiding the need for signal inversion and reducing power consumption by eliminating the use of clock signal inversion, allowing for smaller transistor sizes and efficient state holding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a p-channel MOS transistor is used to transmit a data signal to a flip-flop input, then the transistor has high drive capability when the input is charged to a high level, but the drive capability is reduced when the input is discharged to a low level due to threshold voltage effects
Solution Approach 1:
The patent applies different transistor types (p-channel vs. n-channel) to different locations in the circuit based on local requirements. Specifically, p-channel MOS transistors are used where high drive capability for high-level signals is needed, while n-channel MOS transistors are used where low-level signal transmission is required, ensuring optimal performance in each local region of the circuit.
Solution Approach 2:
The patent inverts the conventional approach by using n-channel MOS transistors in feedback paths instead of p-channel transistors. This inversion allows the feedback path to efficiently transmit low-level signals (which correspond to inverted states) without suffering from threshold voltage effects that plague p-channel transistors when trying to discharge to low levels.
2Power
If larger p-channel MOS transistors are used in feedback paths to ensure state inversion, then the drive capability is improved, but the chip size increases
Solution Approach 1:
The patent optimizes transistor sizing locally based on functional requirements. By using n-channel MOS transistors in feedback paths where low-level signal transmission is critical, the circuit achieves reliable state inversion with smaller transistor dimensions, thereby reducing overall chip area while maintaining drive capability.
3Adaptability or versatility
If clock signal inversion is implemented using an inverter, then the clock signal with opposite phase is generated, but power consumption increases
Solution Approach 1:
The patent extracts and removes the dedicated clock inversion inverter from the circuit architecture. Instead of generating opposite-phase clock signals through active inversion, the design uses the original clock signal directly to control MOS transistor gates, eliminating the energy-consuming inversion step while still achieving the required functionality through alternative circuit mechanisms.
Data Source
AI summary
To provide a miniaturized data holding circuit. First and second MOS transistors respectively transmit a data signal and an inverted data signal to inputs of first and second inverting gates that constitute a state holding circuit when a clock signal is at a first level. Fifth and sixth MOS transistors are respectively inserted in a feedback path from an output of the second inverting gate to the input of the first inverting gate and a feedback path from an output of the first inverting gate to the input of the second inverting gate, and respectively transmit the outputs of the second and first inverting gates when the clock signal is at a second signal level. Seventh and eighth MOS transistors are constituted in a channel of a conductive type different from the first MOS transistor and connected in parallel to the fifth and sixth MOS transistors, respectively, and transmit the output of the second inverting gate and the output of the first inverting gate on the basis of the inverted data signal and the data signal, respectively.