Data Input Circuit Drive Clock Signal Generator
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Solution Overview
Problem
High-performance semiconductor memory devices require faster data input and output capabilities than existing single data rate (SDR) synchronous memory devices, necessitating the development of double data rate (DDR) synchronous memory devices that can operate at twice the speed without increasing the external clock signal frequency.
Innovation Solution
A data input circuit comprising a drive clock signal generator, data transmitter, and write driver, which generates and synchronizes drive clock signals to enable efficient data input and output operations, utilizing a data strobe signal sensing circuit to manage write latency and burst signals, thereby optimizing data transfer without additional control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-bit pre-fetch scheme is used to process multi-bit data in parallel, then data transfer speed is improved, but device complexity increases due to additional control signals and circuits
Solution Approach 1:
The drive clock signal generator is designed to perform multiple functions: it generates the drive clock signal for data transmission, provides timing control for the data transmitter and write driver, and enables test operations through controlled driving of global lines. This multi-functionality reduces the need for separate dedicated control circuits, thereby reducing device complexity while maintaining high data transfer speed through multi-bit pre-fetch operations
Solution Approach 2:
The drive clock signal generator autonomously manages the timing and coordination of multiple components (data transmitter, write driver) without requiring external control signals. By self-generating the necessary clock signals and timing control, the system eliminates the complexity associated with external control signal management while preserving the high-speed parallel data processing capability
2Manufacturing precision
If additional control signals are added to manage write latency and burst operations, then data input precision is improved, but device complexity increases
Solution Approach 1:
The drive clock signal generator combines multiple control functions (write latency management, burst operation control, timing synchronization) into a single integrated circuit. This merging of functions allows precise control of data input timing through a unified control mechanism rather than multiple separate control signals, thereby maintaining data input precision while reducing device complexity
Solution Approach 2:
The integrated drive clock signal generator performs multiple control functions simultaneously: it manages write latency by controlling the timing of drive clock signal generation, handles burst operations through configurable signal generation, and provides synchronization for the data transmitter and write driver. This multi-functionality achieves precise data input control without requiring additional dedicated control signals for each function
3Area of stationary object
If layout area is reduced to improve integration density, then manufacturing cost is reduced, but device complexity may increase due to tighter integration
Solution Approach 1:
The patent integrates the drive clock signal generator, data transmitter, and write driver into a tightly coupled configuration within the memory device. By merging these functions into a compact integrated structure, the layout area is reduced while the internal optimization of the drive clock signal generator maintains manageable device complexity through shared resources and coordinated operation
Data Source
AI summary
Data input circuits are provided. The data input circuit includes a drive clock signal generator, a data transmitter and a write driver. The drive clock signal generator is configured to shift and delay a final clock signal generated in response to a pulse of a sampled clock signal and configured to generate a drive clock signal in response to the delayed final clock signal. The data transmitter is configured to output input data signals as write input data signals in response to the drive clock signal. The write driver is configured to receive the write input data signals in response to the drive clock signal to drive signals on global lines.