Data Input Circuit for Nonvolatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As nonvolatile memory devices increase in capacity, the number of page buffers also increases, leading to longer data loading times during program operations, which negatively impacts performance, especially in high-capacity mobile devices that require rapid data processing.
Innovation Solution
A data input circuit configured to receive external data at both rising and falling edges of a data strobe signal, utilizing two internal data buses and D flip-flops to synchronize data transfer with an internal clock, allowing for simultaneous data input at both edges of the clock signal, thereby reducing data loading time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of page buffers is increased to increase memory capacity, then the memory capacity is improved, but the data loading time is increased
Solution Approach 1:
The patent applies periodic action by utilizing both rising and falling edges of the clock signal for data input. The data input circuit is configured to receive external input data at both rising edges and falling edges of a data strobe signal, effectively doubling the data input frequency and reducing the time required to load data into page buffers while maintaining high memory capacity
Solution Approach 2:
The patent implements dynamics by making the data input circuit adaptable to operate at different clock edges. The circuit dynamically switches between rising edge triggering, falling edge triggering, or both, allowing the system to optimize data loading speed according to operational requirements while supporting increased page buffer counts for high-capacity memory
2Device complexity
If data is input only at rising edges of clock signal, then the circuit operation is simplified, but the data input speed is limited
Solution Approach 1:
The patent utilizes periodic action by capturing data at both rising and falling edges of the clock signal. This approach doubles the effective data input rate compared to single-edge triggering, significantly improving data input speed while the patent manages the resulting circuit complexity through systematic design of the data input circuit
Data Source
AI summary
A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe signal and output the external data as first internal data in response to an internal clock. The second data input unit is configured to receive the external data at falling edges of the data strobe signal and output the external data as second internal data in response to the internal clock. The clock unit is configured to generate the internal clock using an external clock signal.