Data Integrated Circuit Timing Adjustment for Display Signal Delay
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Solution Overview
Problem
Display devices experience signal delay in the delivery path of gate driving signals, leading to uneven charging rates of liquid crystal capacitors, which affects image quality.
Innovation Solution
A data integrated circuit is designed to adjust the output timing of data voltages by using a shift register, latch circuit, and clock generator to output latch clock signals, latch image signals, and divide main clock signals into latch output signals, ensuring that at least two latch output signals are activated at different time intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate driving signals are outputted from the gate driving circuit to drive the display panel, then the display panel can be driven, but signal delay occurs on the delivery path causing uneven charging rates of liquid crystal capacitors
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-adjusting the data voltage output timing based on the distance from the gate driving circuit. The timing adjustment unit determines different output timings for data voltages corresponding to different data lines, with closer data lines receiving voltages earlier than farther ones. This compensates for the signal delay that will occur during actual operation, ensuring uniform charging rates across all liquid crystal capacitors.
Solution Approach 2:
The patent changes the timing parameter of data voltage output based on the position of data lines. The timing adjustment unit modifies the output timing of data voltages according to the distance from the gate driving circuit, creating position-dependent timing adjustments. This parameter change compensates for signal delay and ensures that all liquid crystal capacitors receive their data voltages at the optimal moment for uniform charging.
2Device complexity
If data voltages are outputted simultaneously to all data lines, then the data driving circuit is simple, but liquid crystal capacitors farther from the gate driving circuit charge at lower rates
Solution Approach 1:
The patent introduces dynamics by making the data voltage output timing adaptive rather than fixed. The timing adjustment unit dynamically adjusts the output timing of data voltages based on the position of each data line relative to the gate driving circuit. This dynamic timing adjustment ensures that all liquid crystal capacitors receive their data voltages at the optimal moment, achieving uniform charging rates without requiring complex additional hardware.
3Ease of operation
If the data driving circuit outputs data voltages without timing adjustment, then the circuit operation is simple, but image quality becomes uneven due to signal delay
Solution Approach 1:
The patent implements feedback by having the timing adjustment unit continuously monitor and adjust data voltage output timings based on the actual signal delay characteristics of different data lines. This feedback mechanism ensures that timing adjustments are made to compensate for signal delay while maintaining image quality uniformity, balancing operational simplicity with manufacturing precision.
Data Source
AI summary
Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals